save me avx512...
avx512... save me......
avx512... save me......
all x86 extensions are a ploy by big intel to force you to upgrade
February 1, 2025 at 6:25 PM
save me avx512...
avx512... save me......
avx512... save me......
update. guess who doesnt have avx512
September 24, 2026 at 4:39 AM
update. guess who doesnt have avx512
It's a grand tradition I proudly uphold.
July 26, 2026 at 4:47 AM
It's a grand tradition I proudly uphold.
December 10, 2024 at 8:03 PM
This #AVX512 implementation suggests that the 6 FPU port in #CoyoteCove delivers 6x256b / 3x512b peak FP performance, which is +50% compared to single-chip mobile #AMD #Zen6 #Medusa (4x256b) and -25% compared to desktop #Zen6 #OlympicRidge (4x512b).
#Intel perf + #NovaLake:
bsky.app/profile/inst...
#Intel perf + #NovaLake:
bsky.app/profile/inst...
September 27, 2026 at 6:07 PM
This #AVX512 implementation suggests that the 6 FPU port in #CoyoteCove delivers 6x256b / 3x512b peak FP performance, which is +50% compared to single-chip mobile #AMD #Zen6 #Medusa (4x256b) and -25% compared to desktop #Zen6 #OlympicRidge (4x512b).
#Intel perf + #NovaLake:
bsky.app/profile/inst...
#Intel perf + #NovaLake:
bsky.app/profile/inst...
instead of an NPU we should get 32 core CPUs with a new ARM instruction that makes AVX512 look tiny. retvrn to vector processor
brand new NPU so you can still disable Siri the first moment you can login to the computer
May 7, 2024 at 5:43 PM
instead of an NPU we should get 32 core CPUs with a new ARM instruction that makes AVX512 look tiny. retvrn to vector processor
#AMD #Zen6 -updated
#AVX512 / #AMX Euler-diagram:
" #AVX512_VP2INTERSECT will continue to be supported in AMD processors going forward "
Source:
x.com/LeslieB82382...
GItHub:
github.com/InstLatx64/I...
#AVX512 / #AMX Euler-diagram:
" #AVX512_VP2INTERSECT will continue to be supported in AMD processors going forward "
Source:
x.com/LeslieB82382...
GItHub:
github.com/InstLatx64/I...
February 15, 2025 at 10:44 PM
#AMD #Zen6 -updated
#AVX512 / #AMX Euler-diagram:
" #AVX512_VP2INTERSECT will continue to be supported in AMD processors going forward "
Source:
x.com/LeslieB82382...
GItHub:
github.com/InstLatx64/I...
#AVX512 / #AMX Euler-diagram:
" #AVX512_VP2INTERSECT will continue to be supported in AMD processors going forward "
Source:
x.com/LeslieB82382...
GItHub:
github.com/InstLatx64/I...
the AVX512 x86 extension feels like it was just specifically made for emulating the PS3 sometimes
November 27, 2025 at 2:03 PM
the AVX512 x86 extension feels like it was just specifically made for emulating the PS3 sometimes
named after an xeon phi avx512 mnemonic
November 19, 2025 at 2:38 AM
named after an xeon phi avx512 mnemonic
AMD "Zen 6" ISA to Bring AVX512 FP16, VNNI INT8, and More to Desktop PCs
www.techpowerup.com
November 10, 2025 at 9:46 AM
kinda wild that intel couldnt find a way to make avx512 work with the e cores
February 22, 2026 at 5:42 AM
kinda wild that intel couldnt find a way to make avx512 work with the e cores
#Intel projects 2025+ v50
#PantherLake #NovaLakeU #NovaLakeS #RazerLake #TitanLake #BartlettLake #WildcatLake #GraniteRapids #GraniteRapidsD #DiamondRapids #DiamondRapidsD #CoralRapids #ClearwaterForest #RogueRiverForest #APX #AVX10_1 #AVX10_2 #AVX512
#PantherLake #NovaLakeU #NovaLakeS #RazerLake #TitanLake #BartlettLake #WildcatLake #GraniteRapids #GraniteRapidsD #DiamondRapids #DiamondRapidsD #CoralRapids #ClearwaterForest #RogueRiverForest #APX #AVX10_1 #AVX10_2 #AVX512
July 17, 2025 at 9:08 AM
https://buff.ly/40KmT0t
Graal compiler: +10% faster inference with the latest early access build.
New features: batched prompt processing & AVX512 support.
Graal compiler: +10% faster inference with the latest early access build.
New features: batched prompt processing & AVX512 support.
GitHub - mukel/llama3.java: Practical Llama 3 inference in Java
Practical Llama 3 inference in Java. Contribute to mukel/llama3.java development by creating an account on GitHub.
buff.ly
November 16, 2024 at 4:59 PM
https://buff.ly/40KmT0t
Graal compiler: +10% faster inference with the latest early access build.
New features: batched prompt processing & AVX512 support.
Graal compiler: +10% faster inference with the latest early access build.
New features: batched prompt processing & AVX512 support.
When rustc 1.89 is released next week, Graviola is going to shift to that as its MSRV to take advantage of AVX512 intrinsics being stabilised. If your CPU has AVX512 support, AES-256-GCM speed will improve to about 8.9GiB/s (from about 5.2 now) as measured on a random AMD CPU.
July 29, 2025 at 8:00 PM
When rustc 1.89 is released next week, Graviola is going to shift to that as its MSRV to take advantage of AVX512 intrinsics being stabilised. If your CPU has AVX512 support, AES-256-GCM speed will improve to about 8.9GiB/s (from about 5.2 now) as measured on a random AMD CPU.
I'm in the would-have-been last blog post of Citra from a year ago 😔
azahar-emu.org/blog/one-yea...
#programming
azahar-emu.org/blog/one-yea...
#programming
March 4, 2025 at 5:30 PM
I'm in the would-have-been last blog post of Citra from a year ago 😔
azahar-emu.org/blog/one-yea...
#programming
azahar-emu.org/blog/one-yea...
#programming
I have discovered that my VPS supports AVX512
let the SIMD microoptimization continue
let the SIMD microoptimization continue
March 19, 2026 at 11:08 AM
I have discovered that my VPS supports AVX512
let the SIMD microoptimization continue
let the SIMD microoptimization continue
Remote debugging session:
First time I used gdb, to find crashes on my server in the avx512 version of simd-minimizers.
Conclusion so far is that it's 20% slower than AVX2 🫤
First time I used gdb, to find crashes on my server in the avx512 version of simd-minimizers.
Conclusion so far is that it's 20% slower than AVX2 🫤
May 10, 2025 at 5:20 PM
Remote debugging session:
First time I used gdb, to find crashes on my server in the avx512 version of simd-minimizers.
Conclusion so far is that it's 20% slower than AVX2 🫤
First time I used gdb, to find crashes on my server in the avx512 version of simd-minimizers.
Conclusion so far is that it's 20% slower than AVX2 🫤
January 14, 2025 at 8:39 PM
Steam Machine is a customized _Zen 4_ chip with AVX512 too 🙏🥺
This MEANS something to me
This MEANS something to me
November 12, 2025 at 6:47 PM
Steam Machine is a customized _Zen 4_ chip with AVX512 too 🙏🥺
This MEANS something to me
This MEANS something to me
The two biggest features in this release are:
1) The brand new layer rendering engine that now uses 32-bit floating point instead of 8-bit integer, and is fully AVX2/AVX512 optimized
2) Brand new modernized FileType plugin system. Fully aware of high bit-depths and color mgmt.
1) The brand new layer rendering engine that now uses 32-bit floating point instead of 8-bit integer, and is fully AVX2/AVX512 optimized
2) Brand new modernized FileType plugin system. Fully aware of high bit-depths and color mgmt.
May 10, 2026 at 1:31 AM
The two biggest features in this release are:
1) The brand new layer rendering engine that now uses 32-bit floating point instead of 8-bit integer, and is fully AVX2/AVX512 optimized
2) Brand new modernized FileType plugin system. Fully aware of high bit-depths and color mgmt.
1) The brand new layer rendering engine that now uses 32-bit floating point instead of 8-bit integer, and is fully AVX2/AVX512 optimized
2) Brand new modernized FileType plugin system. Fully aware of high bit-depths and color mgmt.
Oh, and a lot of AVX2, AVX512, and ARM64 optimizations! 5.2 on an AVX512-capable system will be quite the screamer, I've gotten some rather big performance gains out of it.
More details to come ...
More details to come ...
May 20, 2025 at 1:34 AM
Oh, and a lot of AVX2, AVX512, and ARM64 optimizations! 5.2 on an AVX512-capable system will be quite the screamer, I've gotten some rather big performance gains out of it.
More details to come ...
More details to come ...
How do you test code that a CI machine won't run? To support avx-512 SIMD instructions in zlib-rs, we taught Miri how to emulate them.
trifectatech.org/blog/emulati...
#rustlang
trifectatech.org/blog/emulati...
#rustlang
Emulating avx-512 intrinsics in Miri - Trifecta Tech Foundation
Recently we've started work on using more avx512 features in zlib-rs. The avx512 family of target features provides SIMD intrinsics that use 512-bit vectors (double the size of avx2, which uses…
trifectatech.org
December 9, 2025 at 10:31 AM
How do you test code that a CI machine won't run? To support avx-512 SIMD instructions in zlib-rs, we taught Miri how to emulate them.
trifectatech.org/blog/emulati...
#rustlang
trifectatech.org/blog/emulati...
#rustlang
Per Leslie Barnes (AMD CVP and Cores architect) it looks like we’re committing to keeping the #AVX512 VP2INTERSECT instruction. Also, the instruction only takes a single cycle 🥹
x.com/leslieb82382...
x.com/leslieb82382...
February 15, 2025 at 11:55 PM
Per Leslie Barnes (AMD CVP and Cores architect) it looks like we’re committing to keeping the #AVX512 VP2INTERSECT instruction. Also, the instruction only takes a single cycle 🥹
x.com/leslieb82382...
x.com/leslieb82382...
The most underutilized #AVX512 instruction, VPSHUFBITQMB, is actually very useful for compactly generating a mask with arbitrary criteria based on b[5:0], e.g. to select special characters for parsing: if the second operand is a broadcasted 64-bit vector, where the ones represent the searched values
May 17, 2025 at 6:59 PM
The most underutilized #AVX512 instruction, VPSHUFBITQMB, is actually very useful for compactly generating a mask with arbitrary criteria based on b[5:0], e.g. to select special characters for parsing: if the second operand is a broadcasted 64-bit vector, where the ones represent the searched values