AMD宣布針對既有基礎設施升級AI推論提供基於CDNA4架構的Instinct MI350P介面加速器，採用通用的PCIe介面，強調相對競品的每美金每秒Token產生量高出4.2倍。搭載144GB HBM3e的邊際AI推論加速器▲Instinct MI350P可視為規格砍半的Instinct MI450，保有HBM3E記憶體與改採通用的PCIe Gen 5介面與風冷設計Instinct MI350P可視為採用PCIe Gen 5介面的單運算晶粒封裝版的Instinct MI350X，基於CDNA4與台積電3nm/6nm的混合多晶粒封裝，具備8,192個流處理器，具備4.6PFLOPS的MXFP

Derive MI355X GPU (CDNA4) occupancy by hand: the four limiters, MXFP8 GEMM examples, and why matrix-bound kernels hit peak throughput at low occupancy.

YouTube video by SK World Punjabi

A from-first-principles guide to wavefront occupancy on AMD's MI355X (CDNA4): the hardware resource budget, the four limiters that cap it, worked MXFP8 GEMM examples, and why peak throughput often lives at low occupancy.

A from-first-principles guide to wavefront occupancy on AMD's MI355X (CDNA4): the hardware resource budget, the four limiters that cap it, worked MXFP8 GEMM examples, and why peak throughput often lives at low occupancy.

YouTube video by SK World Punjabi

AMD a présenté son nouveau GPU pour l’intelligence artificielle MI350X en 2024, puis en version plus haut de gamme avec un refroidissement liquide avec le MI355X. Les deux exploitent l’architecture maison CDNA4. Le fabricant vient de présenter une nouvelle version : Instinct MI350P, qui se distingue avec un format PCIe paré pour être installé dans […]

YouTube video by SK World Punjabi

This blog post explains how to use Matrix Cores on CDNA3 and CDNA4 architecture, with a focus on low-precision data types such as FP16, FP8, and FP4

In this blog post, we walk through how to use Matrix Cores in HIP kernels, with a focus on low-precision data types such as FP16, FP8, and FP4, as well as the new family of Matrix Core instructions with exponent block scaling introduced in the AMD CDNA™4 architecture. Through code examples and illustrations, we provide the necessary knowledge to start programming Matrix Cores, covering modern low-precision floating-point types, the Matrix Core compiler intrinsics, and the data layouts required by the Matrix Core instructions.

In this blog post, we walk through how to use Matrix Cores in HIP kernels, with a focus on low-precision data types such as FP16, FP8, and FP4, as well as the new family of Matrix Core instructions with exponent block scaling introduced in the AMD CDNA™4 architecture. Through code examples and illustrations, we provide the necessary knowledge to start programming Matrix Cores, covering modern low-precision floating-point types, the Matrix Core compiler intrinsics, and the data layouts required by the Matrix Core instructions.

In this blog post, we walk through how to use Matrix Cores in HIP kernels, with a focus on low-precision data types such as FP16, FP8, and FP4, as well as the new family of Matrix Core instructions with exponent block scaling introduced in the AMD CDNA™4 architecture. Through code examples and illus

In this blog post, we walk through how to use Matrix Cores in HIP kernels, with a focus on low-precision data types such as FP16, FP8, and FP4, as well as the new family of Matrix Core instructions with exponent block scaling introduced in the AMD CDNA™4 architecture. Through code examples and illustrations, we provide the necessary knowledge to start programming Matrix Cores, covering modern low-precision floating-point types, the Matrix Core compiler intrinsics, and the data layouts required by the Matrix Core instructions.

In this blog post, we walk through how to use Matrix Cores in HIP kernels, with a focus on low-precision data types such as FP16, FP8, and FP4, as well as the new family of Matrix Core instructions with exponent block scaling introduced in the AMD CDNA™4 architecture. Through code examples and illustrations, we provide the necessary knowledge to start programming Matrix Cores, covering modern low-precision floating-point types, the Matrix Core compiler intrinsics, and the data layouts required by the Matrix Core instructions.

In this blog post, we walk through how to use Matrix Cores in HIP kernels, with a focus on low-precision data types such as FP16, FP8, and FP4, as well as the new family of Matrix Core instructions with exponent block scaling introduced in the AMD CDNA™4 architecture. Through code examples and illustrations, we provide the necessary knowledge to start programming Matrix Cores, covering modern low-precision floating-point types, the Matrix Core compiler intrinsics, and the data layouts required by the Matrix Core instructions.