No FPGA for me today 😢, so I'd appreciate hearing about your hardware projects. #FPGAFriday
August 22, 2025 at 9:44 AM
No FPGA for me today 😢, so I'd appreciate hearing about your hardware projects. #FPGAFriday
Looking promising. Here the #riscv CPU is updating the text scrolling register. There’s CDC from system to pixel clock domain. #FPGAFriday
June 5, 2026 at 1:51 PM
Looking promising. Here the #riscv CPU is updating the text scrolling register. There’s CDC from system to pixel clock domain. #FPGAFriday
Got time to add more letters on the train yesterday. Happy #FPGAFriday.
May 2, 2025 at 10:03 AM
Got time to add more letters on the train yesterday. Happy #FPGAFriday.
It's about time I updated my recommended #FPGA links. Send me a suggestion this #FPGAFriday. 😊 projectf.io/recommended-...
Recommended FPGA Sites
This page collects some of my favourite FPGA resources from across the Internet.
FPGA Learning Resources Black Mesa Labs FPGA Tutorial Bruno Levy’s Learn FPGA fpga4fun.com fpgacpu.ca Nandland Project ...
projectf.io
March 21, 2025 at 9:58 AM
It's about time I updated my recommended #FPGA links. Send me a suggestion this #FPGAFriday. 😊 projectf.io/recommended-...
Hello hardware friends, it's a hot #FPGAFriday on the south coast. I'm writing tests and docs today, which is surprisingly satisfying if it's for a project you care about.
What are you working on today?
What are you working on today?
June 20, 2025 at 9:43 AM
Hello hardware friends, it's a hot #FPGAFriday on the south coast. I'm writing tests and docs today, which is surprisingly satisfying if it's for a project you care about.
What are you working on today?
What are you working on today?
Fearlessly generate your own clocks with Lattice ECP5 #FPGAs and Yosys. Includes worked examples for #ULX3S and easy to adapt to any dev board. Happy #FPGAFriday! @yosyshq.com projectf.io/posts/ecp5-f...
ECP5 FPGA Clock Generation
Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL (phase-locked loop), you’re stuck running at the speed of your dev board oscillator. This post outl...
projectf.io
January 31, 2025 at 9:42 AM
Fearlessly generate your own clocks with Lattice ECP5 #FPGAs and Yosys. Includes worked examples for #ULX3S and easy to adapt to any dev board. Happy #FPGAFriday! @yosyshq.com projectf.io/posts/ecp5-f...
Happy #FPGAFriday. The hardware for the next installment of 🏝️ Isle #FPGA Computer is ready; now I'm working on docs, a new blog post, and an update for my sponsors. I'm aiming for a public update next Friday. [1/2]
September 26, 2025 at 10:56 AM
Happy #FPGAFriday. The hardware for the next installment of 🏝️ Isle #FPGA Computer is ready; now I'm working on docs, a new blog post, and an update for my sponsors. I'm aiming for a public update next Friday. [1/2]
Happy #FPGAFriday. I'm starting work on the next part of 🏝️Isle #FPGA Computer. I'm looking at input and the early system library. UTF-8 is surprisingly easy to decode in assembler; that's not some sort of humble brag, it's a testament to the design of UTF-8.
January 29, 2026 at 4:19 PM
Happy #FPGAFriday. I'm starting work on the next part of 🏝️Isle #FPGA Computer. I'm looking at input and the early system library. UTF-8 is surprisingly easy to decode in assembler; that's not some sort of humble brag, it's a testament to the design of UTF-8.
Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S
March 19, 2026 at 5:13 PM
Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S
Just merged a signal renaming in 🏝️ Isle.Computer graphics Verilog modules. I only realised how horrible the old naming was when I took the time to review it properly. #FPGAFriday
github.com/projf/isle/p...
github.com/projf/isle/p...
Graphics Signal Renaming by WillGreen · Pull Request #48 · projf/isle
Naming is hard and as the graphics designs have evolved, the signal names have become increasing inconsistent and confusing. I was using the addr suffix for things that weren't addresses (the p...
github.com
July 10, 2026 at 9:50 AM
Just merged a signal renaming in 🏝️ Isle.Computer graphics Verilog modules. I only realised how horrible the old naming was when I took the time to review it properly. #FPGAFriday
github.com/projf/isle/p...
github.com/projf/isle/p...
I've just updated 🏝️Isle chapter 6 software. It's exciting to work on big designs and graphics engines, but building a usable computer is about the small things too. #FPGAFriday
github.com/projf/isle/t...
github.com/projf/isle/t...
March 27, 2026 at 1:52 PM
I've just updated 🏝️Isle chapter 6 software. It's exciting to work on big designs and graphics engines, but building a usable computer is about the small things too. #FPGAFriday
github.com/projf/isle/t...
github.com/projf/isle/t...