Weebit Nano launched its Matrix In-Memory Compute Research Program, giving researchers access to real ReRAM silicon to explore new AI computing architectures. Early results suggest big improvements in power efficiency & latency, especially for edge AI inference. www.jonpeddie.com/news/weebit-...
Weebit Nano opens ReRAM silicon to researchers exploring in-memory AI
Research platform enables exploration of AI architectures with potential for significant power savings.
www.jonpeddie.com
November 4, 2026 at 6:44 PM
Weebit Nano launched its Matrix In-Memory Compute Research Program, giving researchers access to real ReRAM silicon to explore new AI computing architectures. Early results suggest big improvements in power efficiency & latency, especially for edge AI inference. www.jonpeddie.com/news/weebit-...
Weebit Nano launches Weebit Matrix™ In-Memory Compute Research Program
https://ohsem.me/2026/11/weebit-nano-launches-weebit-matrix-tm-in-memory-compute-research-program/?utm_source=bluesky&utm_medium=social
https://ohsem.me/2026/11/weebit-nano-launches-weebit-matrix-tm-in-memory-compute-research-program/?utm_source=bluesky&utm_medium=social
Weebit Nano launches Weebit Matrix™ In-Memory Compute Research Program
Weebit Nano has launched the Weebit Matrix™ In-Memory Compute Research Program, giving industry and academic researchers a ReRAM-based hardware development kit to explore and prototype in-memory compute algorithms and systems for next-generation AI architectures.
ohsem.me
November 5, 2026 at 3:30 AM
Weebit Nano launches Weebit Matrix™ In-Memory Compute Research Program
https://ohsem.me/2026/11/weebit-nano-launches-weebit-matrix-tm-in-memory-compute-research-program/?utm_source=bluesky&utm_medium=social
https://ohsem.me/2026/11/weebit-nano-launches-weebit-matrix-tm-in-memory-compute-research-program/?utm_source=bluesky&utm_medium=social
Aniseh Dorostkar, Hamed Farbeh, Hamid R. Zarandi: ReSAFT: An Efficient Stuck-at Fault-Tolerant Scheme for ReRAM-based Process-in-Memory Accelerators https://arxiv.org/abs/2610.09999 https://arxiv.org/pdf/2610.09999 https://arxiv.org/html/2610.09999
October 8, 2026 at 6:38 AM
Aniseh Dorostkar, Hamed Farbeh, Hamid R. Zarandi: ReSAFT: An Efficient Stuck-at Fault-Tolerant Scheme for ReRAM-based Process-in-Memory Accelerators https://arxiv.org/abs/2610.09999 https://arxiv.org/pdf/2610.09999 https://arxiv.org/html/2610.09999
Aniseh Dorostkar, Hamed Farbeh, Hamid R. Zarandi: An Empirical Fault Vulnerability Exploration of ReRAM-based Process-in-Memory CNN Accelerators https://arxiv.org/abs/2610.07029 https://arxiv.org/pdf/2610.07029 https://arxiv.org/html/2610.07029
October 7, 2026 at 6:38 AM
Aniseh Dorostkar, Hamed Farbeh, Hamid R. Zarandi: An Empirical Fault Vulnerability Exploration of ReRAM-based Process-in-Memory CNN Accelerators https://arxiv.org/abs/2610.07029 https://arxiv.org/pdf/2610.07029 https://arxiv.org/html/2610.07029
Peng Dang, Yintao He, Huawei Li: VARA: A Voltage-Aware ReRAM-Based Accelerator for Energy-Efficient Computing https://arxiv.org/abs/2609.00421 https://arxiv.org/pdf/2609.00421 https://arxiv.org/html/2609.00421
September 2, 2026 at 6:38 AM
Peng Dang, Yintao He, Huawei Li: VARA: A Voltage-Aware ReRAM-Based Accelerator for Energy-Efficient Computing https://arxiv.org/abs/2609.00421 https://arxiv.org/pdf/2609.00421 https://arxiv.org/html/2609.00421
Wooseok Choi, et al.: Update Disturbance-Resilient Analog ReRAM Crossbar Arrays for In-Memory Deep Learning Accelerators https://arxiv.org/abs/2608.25781 https://arxiv.org/pdf/2608.25781 https://arxiv.org/html/2608.25781
August 27, 2026 at 6:40 AM
Wooseok Choi, et al.: Update Disturbance-Resilient Analog ReRAM Crossbar Arrays for In-Memory Deep Learning Accelerators https://arxiv.org/abs/2608.25781 https://arxiv.org/pdf/2608.25781 https://arxiv.org/html/2608.25781
Matteo Galetta, et al.: Study of Resistive Switching Dynamics and Memory States Equilibria in Analog Filamentary Conductive-Metal-Oxide/HfOx ReRAM via Compact Modeling https://arxiv.org/abs/2608.25767 https://arxiv.org/pdf/2608.25767 https://arxiv.org/html/2608.25767
August 27, 2026 at 6:40 AM
Matteo Galetta, et al.: Study of Resistive Switching Dynamics and Memory States Equilibria in Analog Filamentary Conductive-Metal-Oxide/HfOx ReRAM via Compact Modeling https://arxiv.org/abs/2608.25767 https://arxiv.org/pdf/2608.25767 https://arxiv.org/html/2608.25767
Our paper in Springer Nature's Journal of Signal Processing Systems on "Multi-Scheduling Crossbar Mapping and Design-Space Exploration of MAGIC-Based ReRAM Arithmetic Circuits for In-Memory Computing" in available #online link.springer.com/article/10.1... @unibremen.bsky.social @springernature.com
August 21, 2026 at 6:46 AM
Our paper in Springer Nature's Journal of Signal Processing Systems on "Multi-Scheduling Crossbar Mapping and Design-Space Exploration of MAGIC-Based ReRAM Arithmetic Circuits for In-Memory Computing" in available #online link.springer.com/article/10.1... @unibremen.bsky.social @springernature.com
The results also show that the H20-attention + ReRAM-FFN system reduces decode TPOT by 1.25–4.0×, 2.4–10.3×, and 2.5–10.4× versus a homogeneous H20 pool.
August 19, 2026 at 6:12 AM
The results also show that the H20-attention + ReRAM-FFN system reduces decode TPOT by 1.25–4.0×, 2.4–10.3×, and 2.5–10.4× versus a homogeneous H20 pool.
In this paper is presented ReXpert, a ReRAM near-memory architecture for the MoE FFN pool that combines bounded core-local multicast pooling, routing-aware placement, and load-aware fetch, and provisions each communication level from the induced traffic.
arxiv.org/pdf/2608.13962
arxiv.org/pdf/2608.13962
August 19, 2026 at 6:12 AM
In this paper is presented ReXpert, a ReRAM near-memory architecture for the MoE FFN pool that combines bounded core-local multicast pooling, routing-aware placement, and load-aware fetch, and provisions each communication level from the induced traffic.
arxiv.org/pdf/2608.13962
arxiv.org/pdf/2608.13962
ReXpert is a ReRAM near-memory architecture optimizing Mixture-of-Experts (MoE) processing in LLMs by enhancing bandwidth density and reducing latency, achieving 20× lower weight-movement energy. This design improves AI inference efficiency without global sharing. https://arxiv.org/abs/2608.13962
MoE Expert Execution in Disaggregated LLM Serving with a High-Bandwidth ReRAM Near-Memory Architecture
ArXiv link for MoE Expert Execution in Disaggregated LLM Serving with a High-Bandwidth ReRAM Near-Memory Architecture
arxiv.org
August 17, 2026 at 2:50 PM
ReXpert is a ReRAM near-memory architecture optimizing Mixture-of-Experts (MoE) processing in LLMs by enhancing bandwidth density and reducing latency, achieving 20× lower weight-movement energy. This design improves AI inference efficiency without global sharing. https://arxiv.org/abs/2608.13962
Shao, Zeng, Yuan, Liao, Zhang, Wang, Cheng, Tsui: MoE Expert Execution in Disaggregated LLM Serving with a High-Bandwidth ReRAM Near-Memory Architecture https://arxiv.org/abs/2608.13962 https://arxiv.org/pdf/2608.13962 https://arxiv.org/html/2608.13962
August 17, 2026 at 6:38 AM
Shao, Zeng, Yuan, Liao, Zhang, Wang, Cheng, Tsui: MoE Expert Execution in Disaggregated LLM Serving with a High-Bandwidth ReRAM Near-Memory Architecture https://arxiv.org/abs/2608.13962 https://arxiv.org/pdf/2608.13962 https://arxiv.org/html/2608.13962
The solution isn't just "faster chips"—it is the collapsing of the layers of abstraction that create the emulation tax.
In-Memory Computing, where the memory cells themselves (using Memristors or ReRAM) perform the logic.
In-Memory Computing, where the memory cells themselves (using Memristors or ReRAM) perform the logic.
April 3, 2026 at 1:41 PM
The solution isn't just "faster chips"—it is the collapsing of the layers of abstraction that create the emulation tax.
In-Memory Computing, where the memory cells themselves (using Memristors or ReRAM) perform the logic.
In-Memory Computing, where the memory cells themselves (using Memristors or ReRAM) perform the logic.
[3/3] partnership), and Zhejiang Zeyi Xinsheng Venture Capital Partnership (limited partnership) are shareholders. According to the official website, Xinyuan Semiconductor focuses on the research and development of new ReRAM storage technology and related chip products.
July 21, 2026 at 3:45 AM
[3/3] partnership), and Zhejiang Zeyi Xinsheng Venture Capital Partnership (limited partnership) are shareholders. According to the official website, Xinyuan Semiconductor focuses on the research and development of new ReRAM storage technology and related chip products.
[3/3] partnership), and Zhejiang Zeyi Xinsheng Venture Capital Partnership (limited partnership) are shareholders. According to the official website, Xinyuan Semiconductor focuses on the research and development of new ReRAM storage technology and related chip products.
July 21, 2026 at 3:45 AM
[3/3] partnership), and Zhejiang Zeyi Xinsheng Venture Capital Partnership (limited partnership) are shareholders. According to the official website, Xinyuan Semiconductor focuses on the research and development of new ReRAM storage technology and related chip products.
Pingcheng Dong, et al.: 31.1 A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Specul... https://arxiv.org/abs/2605.09375 https://arxiv.org/pdf/2605.09375 https://arxiv.org/html/2605.09375
May 12, 2026 at 6:38 AM
Pingcheng Dong, et al.: 31.1 A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Specul... https://arxiv.org/abs/2605.09375 https://arxiv.org/pdf/2605.09375 https://arxiv.org/html/2605.09375
Guan-Cheng Chen, Chieh-Lin Tsai, Pei-Hsuan Tsai, Yuan-Hao Chang: Sensitivity-Aware Mixed-Precision Quantization for ReRAM-based Computing-in-Memory https://arxiv.org/abs/2512.19445 https://arxiv.org/pdf/2512.19445 https://arxiv.org/html/2512.19445
December 23, 2025 at 6:29 AM
Guan-Cheng Chen, Chieh-Lin Tsai, Pei-Hsuan Tsai, Yuan-Hao Chang: Sensitivity-Aware Mixed-Precision Quantization for ReRAM-based Computing-in-Memory https://arxiv.org/abs/2512.19445 https://arxiv.org/pdf/2512.19445 https://arxiv.org/html/2512.19445
Shao, Liao, Yu, Zhao, Li, Huang, He, Tian, Zou, Wang, Cheng, Tsui: DIRC-RAG: Accelerating Edge RAG with Robust High-Density and High-Loading-Bandwidth Digital In-ReRAM Computation https://arxiv.org/abs/2510.25278 https://arxiv.org/pdf/2510.25278 https://arxiv.org/html/2510.25278
October 30, 2025 at 6:29 AM
Shao, Liao, Yu, Zhao, Li, Huang, He, Tian, Zou, Wang, Cheng, Tsui: DIRC-RAG: Accelerating Edge RAG with Robust High-Density and High-Loading-Bandwidth Digital In-ReRAM Computation https://arxiv.org/abs/2510.25278 https://arxiv.org/pdf/2510.25278 https://arxiv.org/html/2510.25278
Yu-Hong Lai, Chieh-Lin Tsai, Wen Sheng Lim, Han-Wen Hu, Tei-Wei Kuo, Yuan-Hao Chang: ReCross: Efficient Embedding Reduction Scheme for In-Memory Computing using ReRAM-Based Crossbar https://arxiv.org/abs/2509.10627 https://arxiv.org/pdf/2509.10627 https://arxiv.org/html/2509.10627
September 16, 2025 at 6:29 AM
Yu-Hong Lai, Chieh-Lin Tsai, Wen Sheng Lim, Han-Wen Hu, Tei-Wei Kuo, Yuan-Hao Chang: ReCross: Efficient Embedding Reduction Scheme for In-Memory Computing using ReRAM-Based Crossbar https://arxiv.org/abs/2509.10627 https://arxiv.org/pdf/2509.10627 https://arxiv.org/html/2509.10627
Fuyuki Kihara, Seiji Uenohara, Satoshi Awamura, Naoko Misawa, Chihiro Matsui, Ken Takeuchi: 4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation https://arxiv.org/abs/2507.13631 https://arxiv.org/pdf/2507.13631 https://arxiv.org/html/2507.13631
July 21, 2025 at 6:29 AM
Fuyuki Kihara, Seiji Uenohara, Satoshi Awamura, Naoko Misawa, Chihiro Matsui, Ken Takeuchi: 4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation https://arxiv.org/abs/2507.13631 https://arxiv.org/pdf/2507.13631 https://arxiv.org/html/2507.13631
incorporating non-volatile memories like MRAM and ReRAM, mitigate these limitations but struggle with a mismatch between fixed computing resources and dynamically changing inference workloads. To address these challenges, this study introduces a [3/6 of https://arxiv.org/abs/2504.01468v1]
April 3, 2025 at 5:54 AM
incorporating non-volatile memories like MRAM and ReRAM, mitigate these limitations but struggle with a mismatch between fixed computing resources and dynamically changing inference workloads. To address these challenges, this study introduces a [3/6 of https://arxiv.org/abs/2504.01468v1]
Memory (DRAM), High-Bandwidth Memory (HBM), and emerging non-volatile memories like Resistive RAM (ReRAM) and Phase-Change Memory (PCM). These technologies are analyzed based on latency, bandwidth, power consumption, [3/6 of https://arxiv.org/abs/2502.16823v1]
February 25, 2025 at 5:54 AM
Memory (DRAM), High-Bandwidth Memory (HBM), and emerging non-volatile memories like Resistive RAM (ReRAM) and Phase-Change Memory (PCM). These technologies are analyzed based on latency, bandwidth, power consumption, [3/6 of https://arxiv.org/abs/2502.16823v1]
100 fois plus rapide, quasi inusable : la ReRAM arrive enfin pour tout changer ! www.generation-nt.com/actualites/m...
100 fois plus rapide, quasi inusable : la ReRAM arrive enfin pour tout changer !
GNT est le portail Hi-Tech français consacré aux nouvelles technologies (internet, logiciel, matériel, mobilité, entreprise) et au jeu vidéo PC et consoles.
www.generation-nt.com
January 20, 2026 at 7:08 AM
100 fois plus rapide, quasi inusable : la ReRAM arrive enfin pour tout changer ! www.generation-nt.com/actualites/m...
Strong radial electric field scaling near nanoscale conductive filaments and the ReRAM resistive switching mechanism
https://arxiv.org/pdf/2602.05067
Robin Jacobs-Gedrim et al.
https://arxiv.org/pdf/2602.05067
Robin Jacobs-Gedrim et al.
https://arxiv.org/abs/2602.05067
arXiv abstract link
arxiv.org
February 6, 2026 at 4:34 AM
Strong radial electric field scaling near nanoscale conductive filaments and the ReRAM resistive switching mechanism
https://arxiv.org/pdf/2602.05067
Robin Jacobs-Gedrim et al.
https://arxiv.org/pdf/2602.05067
Robin Jacobs-Gedrim et al.