Fun. I might have to yak-shave a crypto protocol crate in order to get it to work on a RP Pico. I keep getting stack overflow HardFaults with the snow crate.

Rolling your own crypto, what could possibly go wrong? (At least I have a spec to follow...)

After poking the PL192 VIC registers in our Cortex-R5F for a few hours and wondering why nothing is happening (and no hardfaults 🤔), remember to double check that the vendor has not replaced the standard interrupt controller with their own 💔 Assumptions is the mother of all ... VIM != VIC

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Turns out the cause was "structs with non-word-sized members on the stack of main". The ram in this mcu has ECC and to perform a <32bit write, it does a read modify write operation which can trigger hardfaults when detecting ECC errors in the read part if the memory location hasn't been initialized

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lol not expected sprintf to be a stopper right now. Hardfaults the mcu for some reason. Is it the rtos? Is it the dma? Blargh

#stm32

Interesting webinar, gdb debugging hard faults on Cortex-M:

https://go.memfault.com/debugging-arm-cortex-m-mcu-webinar?utm_campaign=Debugging%20Cortex%20M%20Webinar&utm_source=blog&utm_medium=Interrupt&utm_term=Debug