I am synthesizing my Verilog design into a Ciclone V (5CSXFC6D6F31C6) and trying to increase FMAX. The design is a SOC (top level) with a processor, a dual port data memory (IPcore), a dual port ROM memory and a UART. I am using the timing closure recommendations to understand where to fix. The top recommendation is about intradomain skew (it says to place source and destination clock on the same global clock resource, always between memory and a register from the processor), but i have already configured the source clock (an input in SOC) as global signal (global clock). I am using a .qsf file for pin assignments, and the clock configuration is as follows: set_location_assignment PIN_AF14 -to CLK set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to CLK Can someone help me with it?