#Intel released the HotChips 2026 conference #DiamondRapids presentation:
cdrdv2-public.intel.com/926846/diamo...
#APX #AMX #AVX10 #PantherCove
cdrdv2-public.intel.com/926846/diamo...
#APX #AMX #AVX10 #PantherCove
August 26, 2026 at 9:47 AM
#Intel released the HotChips 2026 conference #DiamondRapids presentation:
cdrdv2-public.intel.com/926846/diamo...
#APX #AMX #AVX10 #PantherCove
cdrdv2-public.intel.com/926846/diamo...
#APX #AMX #AVX10 #PantherCove
書きました / AVX10とは何だったのか blog.miz-ar.info/2026/08/avx10/
AVX10とは何だったのか | 雑記帳
blog.miz-ar.info
August 21, 2026 at 3:42 AM
書きました / AVX10とは何だったのか blog.miz-ar.info/2026/08/avx10/
So I was mostly just looking into AVX10 while browsing codegen option changes in MSVCs recent release... in my shader toolchain I use AVX2 by default since the amount of xxhash calls I make benefits from that. For my newest render, I just use sse - bc webgpu only does simd128
August 20, 2026 at 6:17 PM
So I was mostly just looking into AVX10 while browsing codegen option changes in MSVCs recent release... in my shader toolchain I use AVX2 by default since the amount of xxhash calls I make benefits from that. For my newest render, I just use sse - bc webgpu only does simd128
That's cool! sadly it seems no amd cpus support avx10 yet. Hopefully one extension becomes standard.
Also are you aiming to support cpus that don't do avx at all? Or is avx a requirement?
Also are you aiming to support cpus that don't do avx at all? Or is avx a requirement?
August 20, 2026 at 5:57 PM
That's cool! sadly it seems no amd cpus support avx10 yet. Hopefully one extension becomes standard.
Also are you aiming to support cpus that don't do avx at all? Or is avx a requirement?
Also are you aiming to support cpus that don't do avx at all? Or is avx a requirement?
avx10 is a superset of avx512 designed to solve exactly this problem, providing many of the same instructions but hopefully avoiding SIGILL when the scheduler takes ur avx instruction using code and swaps it from P to E core
August 20, 2026 at 5:42 PM
avx10 is a superset of avx512 designed to solve exactly this problem, providing many of the same instructions but hopefully avoiding SIGILL when the scheduler takes ur avx instruction using code and swaps it from P to E core
Oh also I think avx10 is the 512 bit registers? Intel discontinued support for that in favor of their stupid e-cores, so you might want to use the 256 bit registers
August 20, 2026 at 5:39 PM
Oh also I think avx10 is the 512 bit registers? Intel discontinued support for that in favor of their stupid e-cores, so you might want to use the 256 bit registers
avx10 makes my head hurt. why intel why
August 20, 2026 at 5:06 PM
avx10 makes my head hurt. why intel why
The x86 Ecosystem Advisory Group refreshed the #ACE (AI Compute Extensions) specification v1.16.2:
x86ecosystem.org/wp-content/u...
#EAG #Intel #AMD #Zen7 #CoralRapids #AVX512 #AVX10 #AMX
x86ecosystem.org/wp-content/u...
#EAG #Intel #AMD #Zen7 #CoralRapids #AVX512 #AVX10 #AMX
August 19, 2026 at 8:49 PM
The x86 Ecosystem Advisory Group refreshed the #ACE (AI Compute Extensions) specification v1.16.2:
x86ecosystem.org/wp-content/u...
#EAG #Intel #AMD #Zen7 #CoralRapids #AVX512 #AVX10 #AMX
x86ecosystem.org/wp-content/u...
#EAG #Intel #AMD #Zen7 #CoralRapids #AVX512 #AVX10 #AMX
AMD Submits AVX10_V2_AUX Support Patches to GCC
#AMD #GCC #AVX10
https://singulism.com/en/2026-07-20-amd-avx10-v2-aux-gcc-patches
#AMD #GCC #AVX10
https://singulism.com/en/2026-07-20-amd-avx10-v2-aux-gcc-patches
AMD Submits AVX10_V2_AUX Support Patches to GCC
AMD's compiler engineer has submitted patches to GCC to support the AVX10_V2_AUX ISA, adding instructions for converting compressed data formats like FP4 and FP6, aimed at accelerating AI workloads. T
singulism.com
July 20, 2026 at 5:21 PM
AMD Submits AVX10_V2_AUX Support Patches to GCC
#AMD #GCC #AVX10
https://singulism.com/en/2026-07-20-amd-avx10-v2-aux-gcc-patches
#AMD #GCC #AVX10
https://singulism.com/en/2026-07-20-amd-avx10-v2-aux-gcc-patches
AMD Posts AVX10_V2_AUX ISA Support Patches For GCC Compiler
https://www.phoronix.com/news/GCC-AVX10-V2-AUX-Patches
https://www.phoronix.com/news/GCC-AVX10-V2-AUX-Patches
July 20, 2026 at 11:00 AM
AMD Posts AVX10_V2_AUX ISA Support Patches For GCC Compiler
https://www.phoronix.com/news/GCC-AVX10-V2-AUX-Patches
https://www.phoronix.com/news/GCC-AVX10-V2-AUX-Patches
AMD Posts AVX10_V2_AUX ISA Support Patches For GCC Compiler - https://www.phoronix.com/news/GCC-AVX10-V2-AUX-Patches
AMD Posts AVX10_V2_AUX ISA Support Patches For GCC Compiler
Earlier this month Intel compiler engineers posted initial GCC compiler patches for the AI Compute Extensions "ACE" that was born out of the x86 Ecosystem Advisory Group to augment AVX and scalar code with new capabilities for AI/ML workloads. Now as part of that an AMD compiler engineer posted patches over the weekend for AVX10_V2_AUX ISA support...
www.phoronix.com
July 20, 2026 at 10:39 AM
AMD Posts AVX10_V2_AUX ISA Support Patches For GCC Compiler - https://www.phoronix.com/news/GCC-AVX10-V2-AUX-Patches
Intel And AMD Push ACE To Move AI Math Back Onto x86 CPUs
Intel and AMD have released the ACE specification for x86 processors, using AVX10 registers and dedicated matrix-multiplication silicon to make some AI tasks more power-efficient on CPUs rather
#Semiconductors #AI
Link card below.
Intel and AMD have released the ACE specification for x86 processors, using AVX10 registers and dedicated matrix-multiplication silicon to make some AI tasks more power-efficient on CPUs rather
#Semiconductors #AI
Link card below.
Intel And AMD Push ACE To Move AI Math Back Onto x86 CPUs
Intel and AMD have released the ACE specification for x86 processors, using AVX10 registers and dedicated matrix-multiplication silicon to make some AI tasks more power-efficient on CPUs rather than GPUs or NPUs.
stechtimes.com
June 20, 2026 at 3:02 PM
Intel And AMD Push ACE To Move AI Math Back Onto x86 CPUs
Intel and AMD have released the ACE specification for x86 processors, using AVX10 registers and dedicated matrix-multiplication silicon to make some AI tasks more power-efficient on CPUs rather
#Semiconductors #AI
Link card below.
Intel and AMD have released the ACE specification for x86 processors, using AVX10 registers and dedicated matrix-multiplication silicon to make some AI tasks more power-efficient on CPUs rather
#Semiconductors #AI
Link card below.
The x86 Ecosystem Advisory Group released the #ACE (AI Compute Extensions) specification v1.15:
x86ecosystem.org/wp-content/u...
#EAG #Intel #AMD #Zen7 #CoralRapids #AVX512 #AVX10 #AMX
x86ecosystem.org/wp-content/u...
#EAG #Intel #AMD #Zen7 #CoralRapids #AVX512 #AVX10 #AMX
June 18, 2026 at 9:08 AM
The x86 Ecosystem Advisory Group released the #ACE (AI Compute Extensions) specification v1.15:
x86ecosystem.org/wp-content/u...
#EAG #Intel #AMD #Zen7 #CoralRapids #AVX512 #AVX10 #AMX
x86ecosystem.org/wp-content/u...
#EAG #Intel #AMD #Zen7 #CoralRapids #AVX512 #AVX10 #AMX
@brouhaha@mastodon.social I'm doing my best to wait for Nova Lake; I think that'll be when I upgrade because for my needs I do expect a performance boost from APX and AVX10.
June 14, 2026 at 12:25 PM
@brouhaha@mastodon.social I'm doing my best to wait for Nova Lake; I think that'll be when I upgrade because for my needs I do expect a performance boost from APX and AVX10.
i dont think i caught when they were talking about this, was this before or after apple silicon? well i guess either way they clearly learned the wrong lessons. AVX10 etc genuinely do seem neat for MoE inference but even then, the applicability/usefulness on a consumer laptop is very, very limited
May 31, 2026 at 8:44 PM
i dont think i caught when they were talking about this, was this before or after apple silicon? well i guess either way they clearly learned the wrong lessons. AVX10 etc genuinely do seem neat for MoE inference but even then, the applicability/usefulness on a consumer laptop is very, very limited
putting TPUs inside of SOCs seems pretty boneheaded now that we have some hindsight, they cant do anything useful (assuming you take for granted that any tensor workload can be useful) and are effectively just a big waste of die space. better off using IGP for matrix operations, or w/e AVX10 does
May 31, 2026 at 8:20 PM
putting TPUs inside of SOCs seems pretty boneheaded now that we have some hindsight, they cant do anything useful (assuming you take for granted that any tensor workload can be useful) and are effectively just a big waste of die space. better off using IGP for matrix operations, or w/e AVX10 does
AMD และ Intel จับมือผลักดันชุดคำสั่ง AI ใหม่บน x86 ชื่อ “ACE” โดยจะรวมเข้ากับ AVX10 www.quickpcmag.com/amd-intel-ac...
AMD และ Intel จับมือผลักดันชุดคำสั่ง AI ใหม่บน x86 ชื่อ “ACE” โดยจะรวมเข้ากับ AVX10 - QuickPC: วิเคราะห์ เจาะลึก Hardware & Software อัปเดตล่าสุด
AMD และ Intel ร่วมกันออกแบบชุดคำสั่ง AI ใหม่สำหรับสถาปัตยกรรม x86 ภายใต้ชื่อ ACE (AI Compute Extensions) พร้อมเผยแพร่เอกสารชุดแรกแล้ว
www.quickpcmag.com
May 5, 2026 at 5:30 AM
AMD และ Intel จับมือผลักดันชุดคำสั่ง AI ใหม่บน x86 ชื่อ “ACE” โดยจะรวมเข้ากับ AVX10 www.quickpcmag.com/amd-intel-ac...
AVX-512 FP16 対応してたらよかったなーって思ってたけど、すでに後継の AVX10 があるのか
May 4, 2026 at 3:40 PM
AVX-512 FP16 対応してたらよかったなーって思ってたけど、すでに後継の AVX10 があるのか
През октомври 2024 година AMD и Intel съвместно създадоха Консултативната група за екосистемата x86 (x86 Ecosystem Advisory Group, EAG), обединявайки водещите участници в бранша с цел да насърчат бъдещето на x86 изчислителната архитектура...
AMD и Intel обединиха усилията си: производителността на x86 при матрични изчисления се увеличи 16 пъти
През октомври 2024 година AMD и Intel съвместно създадоха Консултативната група за екосистемата x86 (x86 Ecosystem Advisory Group, EAG), обединявайки водещите участници в бранша с цел да насърчат бъдещето на x86 изчислителната архитектура. В момента на създаването на EAG бяха обявени четири ключови функции: FRED, AVX10, ChkTag и ACE. Сега AMD и Intel публикуваха технически документ (бяла книга) за архитектурата ACE, като официално представиха този набор от инструкции, наречен „стандартна матрична ускоряваща архитектура x86“, пред общността на разработчиците. Основната цел на ACE е да осигури скокообразно увеличение на производителността на матричните изчисления на x86 чипове.
www.kaldata.com
April 30, 2026 at 8:48 AM
През октомври 2024 година AMD и Intel съвместно създадоха Консултативната група за екосистемата x86 (x86 Ecosystem Advisory Group, EAG), обединявайки водещите участници в бранша с цел да насърчат бъдещето на x86 изчислителната архитектура...
x86の新AI命令ACE公開、AVX10比16倍の密度。AMDとIntelが共同で書いた最初の答え
AMDとIntel共同運営のx86 EAGが、AI命令ACEの仕様書を2026年4月15日に公開しました。
行列演算の密度はAVX10比で16倍。
Intel独自のAMXと違い、ノートPCからデータセンターまで広がる設計です。
youtu.be/GpqW33mFT8o
#AMD #Intel #x86
x86 ACE specs explained.
AMDとIntel共同運営のx86 EAGが、AI命令ACEの仕様書を2026年4月15日に公開しました。
行列演算の密度はAVX10比で16倍。
Intel独自のAMXと違い、ノートPCからデータセンターまで広がる設計です。
youtu.be/GpqW33mFT8o
#AMD #Intel #x86
x86 ACE specs explained.
April 30, 2026 at 5:49 AM
x86の新AI命令ACE公開、AVX10比16倍の密度。AMDとIntelが共同で書いた最初の答え
AMDとIntel共同運営のx86 EAGが、AI命令ACEの仕様書を2026年4月15日に公開しました。
行列演算の密度はAVX10比で16倍。
Intel独自のAMXと違い、ノートPCからデータセンターまで広がる設計です。
youtu.be/GpqW33mFT8o
#AMD #Intel #x86
x86 ACE specs explained.
AMDとIntel共同運営のx86 EAGが、AI命令ACEの仕様書を2026年4月15日に公開しました。
行列演算の密度はAVX10比で16倍。
Intel独自のAMXと違い、ノートPCからデータセンターまで広がる設計です。
youtu.be/GpqW33mFT8o
#AMD #Intel #x86
x86 ACE specs explained.
x86の新AI命令ACE公開、AVX10比16倍の密度。AMDとIntelが共同で書いた最初の答え /AMX・行列演算・x86 EAG・ホワイト... youtu.be/GpqW33mFT8o?... @YouTubeより
x86の新AI命令ACE公開、AVX10比16倍の密度。AMDとIntelが共同で書いた最初の答え /AMX・行列演算・x86 EAG・ホワイトペーパー
YouTube video by 情報の灯台
youtu.be
April 30, 2026 at 5:49 AM
x86の新AI命令ACE公開、AVX10比16倍の密度。AMDとIntelが共同で書いた最初の答え /AMX・行列演算・x86 EAG・ホワイト... youtu.be/GpqW33mFT8o?... @YouTubeより