LightNews — News, ranked by scholars

InstLatX64

@instlatx64.bsky.social

And of course #Intel can't send into battle #DiamondRapids against #AMD #Venice (4x512b) without enough FPU capabilities

September 29, 2026 at 11:11 AM

InstLatX64

@instlatx64.bsky.social

Given the unique CPUID family (400Fxx), the distinct #PantherCove codename, and #Intel's insistence on distinguishing between server and client cores, I would be surprised if #DiamondRapids did not feature 8x256-bit FPU ports for #AMX, additional FMA and permutation EUs

September 29, 2026 at 11:01 AM

Pulse Of Nations

@pulseofnations.lol

Diamond Rapids brings 256 cores, PCIe Gen6 and drops hyperthreading, but Intel pushes launch back as it targets HPC and agentic AI workloads.

#AiCompute #DiamondRapids #HotChips #Hpc #Intel #PcieGen6 #Server #Xeon

Intel Unveils 256-Core Xeon 7 at Hot Chips, Delays Launch to 2027

Diamond Rapids brings 256 cores, PCIe Gen6 and drops hyperthreading, but Intel pushes launch back as it targets HPC and agentic AI workloads.

pulseofnations.lol

August 26, 2026 at 10:20 PM

Daily CyberSecurity

@securityonline.bsky.social

Intel unveils the Diamond Rapids processor and Crescent Island accelerator at Hot Chips 2026, targeting the complex demands of Agentic AI operations.

#Intel #DiamondRapids #CrescentIsland #AgenticAI #HotChips2026

Intel Unveils Diamond Rapids and Crescent Island

At the prestigious Hot Chips 2026 conference in California, Intel comprehensively revealed the latest evolutionary direction for its server and data center architectures. Generative artificial intelligence is rapidly shifting away from simplistic conversational models. It now increasingly demands complex, multi-step reasoning, intricate tool invocation, and extensive long-context processing. This sophisticated paradigm is commonly known as "Agentic AI." Consequently, Intel publicly disclosed crucial design details…

securityexpress.info

August 26, 2026 at 12:38 PM

InstLatX64

@instlatx64.bsky.social

#Intel released the HotChips 2026 conference #DiamondRapids presentation:
cdrdv2-public.intel.com/926846/diamo...
#APX #AMX #AVX10 #PantherCove

August 26, 2026 at 9:47 AM

InstLatX64

@instlatx64.bsky.social

#Intel refreshed the Advanced Performance Extensions (#Intel #APX) Architecture Specification to 9.0:
cdrdv2-public.intel.com/926860/35582...
#APX #DiamondRapids #NovaLake #PantherCove #CoyoteCove #ArcticWolf

August 26, 2026 at 9:32 AM

TecHCKX

@tecnewshcxk.bsky.social

Diamond RapidsがHot Chipsでお披露目とのことで、ついに来たかという感じ。エージェントAI向けって言葉はどこのベンダーも使うけど、Intelが3アーキテクチャで相互補完する構成にしてきたのは地味に興味深いね。ただメモリ帯域やインターコネクトの詳細がまだ薄くて、実運用でどこまでスケールするかは実機ベンチ待ちかな。個人的には電力効率の実数値が出るまで様子見したい。

#Xeon #DiamondRapids
https://example.com

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August 25, 2026 at 2:00 AM

ComputerBase

@computerbase.de

Intel Diamond Rapids: 256 Kerne, 16 CPU-Tiles, vier Cache-Dies und zwei I/O-Tiles #Intel #DiamondRapids #Hotchips

Intel Diamond Rapids: 256 Kerne, 16 CPU-Tiles, vier Cache-Dies und zwei I/O-Tiles

Intel enthüllt Diamond Rapids: 256 Kerne werden durch 16 CPU-Tiles in 18A-P realisiert, die auf vier Cache-Base-Tiles in Intel 3-T sitzen.

www.computerbase.de

August 24, 2026 at 5:15 PM

Lowyat.NET

@lowyat.bsky.social

Intel Reportedly Cancels 512-Core Diamond Rapids Xeon 7 CPU #diamondrapids #intel #rumoursleaks #xeon7

https://www.lowyat.net/2026/401106/intel-cancels-512-core-cpu/

August 11, 2026 at 12:00 PM

InstLatX64

@instlatx64.bsky.social

#Intel released the SDE 10.13.1 (Software Development Emulator) with x86 EAG #ACE (Al Compute Extensions) support:
www.intel.com/content/www/... #NovaLake #DiamondRapids #APX #AVX10_2

August 4, 2026 at 7:31 AM

InstLatX64

@instlatx64.bsky.social

Another interesting GCC patch: disabling the memory-form of NDD #Intel #APX instructions. #DiamondRapids is not mentioned, perhaps this is an #ArcticWolf related issue?

i386: Add tuning to disable memory-form NDD
gcc.gnu.org/git/?p=gcc.g...

July 11, 2026 at 1:11 PM

InstLatX64

@instlatx64.bsky.social

An interesting #APX GCC patch:
i386: Disable SETcc.ZU generation on DMR/NVL via tune flag
gcc.gnu.org/git/?p=gcc.g...
Strange, isn't a 6 byte EVEX better than a 2/3/4 byte XOR + 3/4 byte SETcc?
#DiamondRapids #NovaLake #PantherCove

July 6, 2026 at 2:27 PM

InstLatX64

@instlatx64.bsky.social

InstLatX64 refresh:
#AMD:
- #MustangPeak #Zen6 #Threadripper [1]
- #Zen7 #GrimlockPoint #GrimlockRidge #GrimlockHalo [2]
- #Zen7 #EPYC #Florence [2]
#Intel
- #PantherLakeR E0652 [3]
- #DiamondRapids 18A-P, HTT Off
- #CoralRapids
#Hygon
- 900F80 Suzhou [4]
GitHub:
github.com/InstLatx64/I...
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June 29, 2026 at 1:37 PM

InstLatX64

@instlatx64.bsky.social

#Intel released the 62nd edition of the ISA Extensions Reference with.
#UTMR and #AMX_TF32 support removed (it means only one instruction: TMMULTF32PS)
Download:
cdrdv2-public.intel.com/922690/31943...
#DiamondRapids #NovaLake #PantherCove #CoyoteCove #ArcticWolf

June 27, 2026 at 9:14 AM

InstLatX64

@instlatx64.bsky.social

#Intel released the SDE 10.8 (Software Development Emulator):
www.intel.com/content/www/...
#NovaLake #DiamondRapids #APX #AVX10_2

March 27, 2026 at 12:10 PM

InstLatX64

@instlatx64.bsky.social

#Intel released the 61st edition of the ISA Extensions Reference with PerfMon Masking and clarifications.
Download:
cdrdv2-public.intel.com/915637/31943...
#DiamondRapids #NovaLake #WildcatLake #PantherCove #CoyoteCove #ArcticWolf
CPUID.07h.01.EDX[22]= #SEC_TEE_ATTESTATION

March 20, 2026 at 5:52 AM

InstLatX64

@instlatx64.bsky.social

My quick note about #Intel
#ArrowLake CPUID C0662 #LionCove
and
#PantherLake CPUID C06C3 #CougarCove
instruction level differences

I hope this is because all resources were directed towards developing #CoyoteCove / #PantherCove in #NovaLake and #Diamondrapids.

March 9, 2026 at 8:05 PM

InstLatX64

@instlatx64.bsky.social

#Intel released the SDE 10.7 (Software Development Emulator) with Indirect Branch History Fence ( #IBHF) instruction support and refreshed CPUID dumps:
www.intel.com/content/www/...
#NovaLake #DiamondRapids #APX #AVX10_2

February 26, 2026 at 9:37 AM

InstLatX64

@instlatx64.bsky.social

#Intel released the SDE 10.5.0 (Software Development Emulator), sync with 60th ISA Ext Guide:
www.intel.com/content/www/...
#NovaLake #DiamondRapids #APX #AVX10_2

February 1, 2026 at 7:24 PM

InstLatX64

@instlatx64.bsky.social

#Intel refreshed the "Intel Resource Director Technology (Intel RDT) Architecture Specification" to 1.3 356688-004
cdrdv2-public.intel.com/851356/35668...
#DiamondRapids

January 6, 2026 at 8:31 PM

InstLatX64

@instlatx64.bsky.social

Another interesting #Intel #DiamondRapids info from Linux kernel list:
It seems DMR has multiple L3 cache, one per #CBB (Core Building Block = CPU die)
lore.kernel.org/all/20251227...

January 1, 2026 at 6:05 PM

InstLatX64

@instlatx64.bsky.social

Insightful Linux kernel patch:
#Intel #DiamondRapids CPU chip = Core Building Block (CBB) and unlike #GraniteRapids they do not have an IMC. #DMR can have a chip with two "Integrated I/O and one memory hub (IMH)". DMR goes even further than #ClearwaterForest where the IMC is on the Base Tile.
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