Sharing our #SC24 demo built in partnership with the @setiinstitute.bsky.social. 100Gbps of streaming #RF data is RDMA’d from RFSoC to CX7 + RTX A6000 where it is then processed + AI inferenced in real-time. AI for real-time instruments is here!
November 24, 2024 at 2:18 PM
Sharing our #SC24 demo built in partnership with the @setiinstitute.bsky.social. 100Gbps of streaming #RF data is RDMA’d from RFSoC to CX7 + RTX A6000 where it is then processed + AI inferenced in real-time. AI for real-time instruments is here!
やっぱりちゃんと自分用のRFSoCを一枚持っておきたい
December 29, 2024 at 3:09 PM
やっぱりちゃんと自分用のRFSoCを一枚持っておきたい
Hey, anyone with access to a relatively recent Zynq US+ (MPSoC or RFSoC, doesn't matter) mind doing a USB capture of the traffic to the FTDI cable when attaching it in Vivado, and also try to dump the scanchain in openocd/bmda?
March 31, 2025 at 6:23 AM
Hey, anyone with access to a relatively recent Zynq US+ (MPSoC or RFSoC, doesn't matter) mind doing a USB capture of the traffic to the FTDI cable when attaching it in Vivado, and also try to dump the scanchain in openocd/bmda?
Leading semiconductor analyst s…
https://www.tomshardware.com/tech-industry/leading-semiconductor-analyst-accuses-amd-of-treason-over-restricted-chips-availability-in-china-amd-blames-diversion-of-export-controlled-rfsoc-usd36-000-radar-silicon-allegedly-quoted-at-usd1-000-for-crowdfunding-project
https://www.tomshardware.com/tech-industry/leading-semiconductor-analyst-accuses-amd-of-treason-over-restricted-chips-availability-in-china-amd-blames-diversion-of-export-controlled-rfsoc-usd36-000-radar-silicon-allegedly-quoted-at-usd1-000-for-crowdfunding-project
September 25, 2026 at 5:29 AM
RF Connectors more or less on the die. RFSoc DAC up to 80GHz Bandwidth and 256GS/s. Just imagine when this will be consumer ware in 10 years. https://youtu.be/rVJwcZavr9U
November 11, 2024 at 5:00 PM
RF Connectors more or less on the die. RFSoc DAC up to 80GHz Bandwidth and 256GS/s. Just imagine when this will be consumer ware in 10 years. https://youtu.be/rVJwcZavr9U
GiamMa-based researchers SDR R&D IoT: #PYNQ example of using the #RFSoC (compatible with PYNQ images v2.6 for the #ZCU111 and #RFSoC2x2) as a #QPSK #radio transceiver #SoftwareDefinedRadios #RFSoC #Xilinx #SoftwareDefinedRadio #MatLab #QPSK #Transceiver
November 19, 2024 at 3:17 PM
GiamMa-based researchers SDR R&D IoT: #PYNQ example of using the #RFSoC (compatible with PYNQ images v2.6 for the #ZCU111 and #RFSoC2x2) as a #QPSK #radio transceiver #SoftwareDefinedRadios #RFSoC #Xilinx #SoftwareDefinedRadio #MatLab #QPSK #Transceiver
direct RF sampling technique of the RFSoC, which significantly simplified the architecture compared to the conventional LLRF. We have extended the frequency range of the NG-LLRF to S-band and experimented with different RFSoC devices and system [3/5 of https://arxiv.org/abs/2505.22876v1]
May 30, 2025 at 6:11 AM
direct RF sampling technique of the RFSoC, which significantly simplified the architecture compared to the conventional LLRF. We have extended the frequency range of the NG-LLRF to S-band and experimented with different RFSoC devices and system [3/5 of https://arxiv.org/abs/2505.22876v1]
The MicroPhase AntSDR T510 AI combines an AMD RFSoC and an NVIDIA Jetson on one board that crushes latency in next-gen wireless development.
The AntSDR T510 AI Puts an AMD RFSoC and an NVIDIA Jetson on One Board
The MicroPhase AntSDR T510 AI combines an AMD RFSoC and an NVIDIA Jetson on one board that crushes latency in next-gen wireless development.
www.hackster.io
June 21, 2026 at 1:17 PM
The MicroPhase AntSDR T510 AI combines an AMD RFSoC and an NVIDIA Jetson on one board that crushes latency in next-gen wireless development.
I would note that there are a number of “rad-hard” FPGA assemblies for space these days that use a rad-hard CPU doing periodic bitstream patrol ECC scrubs and reloading on failure, but in general GPUs tend not to have a lot of those features built in while FPGAs do.
Q8RF RFSoC FAMILY
xiphos.com
December 19, 2025 at 7:59 PM
I would note that there are a number of “rad-hard” FPGA assemblies for space these days that use a rad-hard CPU doing periodic bitstream patrol ECC scrubs and reloading on failure, but in general GPUs tend not to have a lot of those features built in while FPGAs do.
Researchers leverage Xilinx RFSoC tech to boost particle accelerator performance by cutting latency and distortion. What other innovations could advance #ParticlePhysics? #RFTechnology #TechInnovation LINK
October 17, 2025 at 11:26 AM
Researchers leverage Xilinx RFSoC tech to boost particle accelerator performance by cutting latency and distortion. What other innovations could advance #ParticlePhysics? #RFTechnology #TechInnovation LINK
Feed: "CNX Software – Embedded Systems News"
By: Jean-Luc Aufranc (CNXSoft) on Thursday, June 11, 2026
By: Jean-Luc Aufranc (CNXSoft) on Thursday, June 11, 2026
PZSDR P047 RF-ADC and RF-DAC high-end SDR board is based on AMD Zynq UltraScale+ ZU47DR RFSoC (Crowdfunding)
PZSDR P047 RF-ADC and RF-DAC software-defined radio (SDR) board is based on AMD Zynq UltraScale+ ZU47DR RFSoC with a quad-core Cortex-A53 processor, a
www.cnx-software.com
June 11, 2026 at 6:02 PM
Feed: "CNX Software – Embedded Systems News"
By: Jean-Luc Aufranc (CNXSoft) on Thursday, June 11, 2026
By: Jean-Luc Aufranc (CNXSoft) on Thursday, June 11, 2026
Feeling very excited about this new QICK system we got stalled underground! [slaps box top] this bad boy can fit so much continuous usable bandwidth in it https://arxiv.org/abs/2311.17171 🧪
February 8, 2024 at 7:19 AM
Feeling very excited about this new QICK system we got stalled underground! [slaps box top] this bad boy can fit so much continuous usable bandwidth in it https://arxiv.org/abs/2311.17171 🧪
Hatef Nouri, George Sklivanitis, Dimitris A. Pados, Elizabeth Serena Bentley: Demonstration of a 1.2 Gbps Always-on Fully-Connected Mesh Network with RFSoC SDRs https://arxiv.org/abs/2603.06667 https://arxiv.org/pdf/2603.06667 https://arxiv.org/html/2603.06667
March 10, 2026 at 6:33 AM
Hatef Nouri, George Sklivanitis, Dimitris A. Pados, Elizabeth Serena Bentley: Demonstration of a 1.2 Gbps Always-on Fully-Connected Mesh Network with RFSoC SDRs https://arxiv.org/abs/2603.06667 https://arxiv.org/pdf/2603.06667 https://arxiv.org/html/2603.06667
Great work in #QST 🚀 Qibosoq, an #open-source server-side software package designed for radio frequency system on chip (RFSoC) for executing arbitrary pulse sequences on self-hosted #quantum processing units via the Qibo framework
Paper ➡️ iopscience.iop.org/article/10.1...
Paper ➡️ iopscience.iop.org/article/10.1...
May 27, 2025 at 8:52 AM
Great work in #QST 🚀 Qibosoq, an #open-source server-side software package designed for radio frequency system on chip (RFSoC) for executing arbitrary pulse sequences on self-hosted #quantum processing units via the Qibo framework
Paper ➡️ iopscience.iop.org/article/10.1...
Paper ➡️ iopscience.iop.org/article/10.1...
Published in #RASTI RAS Techniques & Instruments: "RFSoC receiver calibration system for 21-cm global spectrum experiments from space: the CosmoCube case", Zhu et al. This is Fig. 6: for the caption & to read the paper please visit academic.oup.com/rasti/articl... @royalastrosoc.bsky.social
February 10, 2025 at 12:02 PM
Published in #RASTI RAS Techniques & Instruments: "RFSoC receiver calibration system for 21-cm global spectrum experiments from space: the CosmoCube case", Zhu et al. This is Fig. 6: for the caption & to read the paper please visit academic.oup.com/rasti/articl... @royalastrosoc.bsky.social
developed based on direct RF sampling technology of RF system-on-chip (RFSoC) devices, RF pulse shaping can be realized without the analogue phase shifters, which can significantly simplify the system architecture. We performed a range of high-power [3/6 of https://arxiv.org/abs/2505.22872v1]
May 30, 2025 at 6:11 AM
developed based on direct RF sampling technology of RF system-on-chip (RFSoC) devices, RF pulse shaping can be realized without the analogue phase shifters, which can significantly simplify the system architecture. We performed a range of high-power [3/6 of https://arxiv.org/abs/2505.22872v1]
FIREQ demonstrates resource-efficient superconducting qubit control via RFSoC FPGAs with direct RF synthesis up to 9.3 GHz. Validated on real qubits: T₁=6.94µs, T₂*=13.50µs. Open-source platform enables scalable quantum processor instrumentation.
#QuantumComputing #SuperconductingQubits #FPGA
#QuantumComputing #SuperconductingQubits #FPGA
FIREQ: An Open-Source FPGA Framework for Superconducting Qubit Control and Readout
iq.fp2.dev
September 1, 2026 at 2:06 AM
FIREQ demonstrates resource-efficient superconducting qubit control via RFSoC FPGAs with direct RF synthesis up to 9.3 GHz. Validated on real qubits: T₁=6.94µs, T₂*=13.50µs. Open-source platform enables scalable quantum processor instrumentation.
#QuantumComputing #SuperconductingQubits #FPGA
#QuantumComputing #SuperconductingQubits #FPGA
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An RFSoC-based Backend and Timing System for the Balloon-borne Very Long Baseline Interferometry Experiment. Mayukh Bagchi et. al. https://arxiv.org/abs/2609.11605
September 11, 2026 at 9:44 PM
An RFSoC-based Backend and Timing System for the Balloon-borne Very Long Baseline Interferometry Experiment. Mayukh Bagchi et. al. https://arxiv.org/abs/2609.11605
An RFSoC-based Backend and Timing System for the Balloon-borne Very Long Baseline Interferometry Experiment
https://arxiv.org/pdf/2609.11605
Mayukh Bagchi et al.
https://arxiv.org/pdf/2609.11605
Mayukh Bagchi et al.
https://arxiv.org/abs/2609.11605
arXiv abstract link
arxiv.org
September 11, 2026 at 4:01 AM
An RFSoC-based Backend and Timing System for the Balloon-borne Very Long Baseline Interferometry Experiment
https://arxiv.org/pdf/2609.11605
Mayukh Bagchi et al.
https://arxiv.org/pdf/2609.11605
Mayukh Bagchi et al.