Recently received a Terasic Atum A3-Nano featuring an Altera Agilex3 FPGA, SDRAM, RGMII, HDMI, and SD-Card.
A great help in validating openFPGALoader support for Agilex devices (Agilex3/5). SRAM programming support is now fully functional.
github.com/trabucayre/o...
A great help in validating openFPGALoader support for Agilex devices (Agilex3/5). SRAM programming support is now fully functional.
github.com/trabucayre/o...
June 21, 2026 at 6:13 AM
Recently received a Terasic Atum A3-Nano featuring an Altera Agilex3 FPGA, SDRAM, RGMII, HDMI, and SD-Card.
A great help in validating openFPGALoader support for Agilex devices (Agilex3/5). SRAM programming support is now fully functional.
github.com/trabucayre/o...
A great help in validating openFPGALoader support for Agilex devices (Agilex3/5). SRAM programming support is now fully functional.
github.com/trabucayre/o...
Isle is open hardware and uses an open-source toolchain (Yosys & nextpnr) for ECP5 #FPGA. With the toolchain installed, it's quick and simple to get Isle running.
For example, text mode (chapter 4) on ULX3S:
cd isle/boards/ulx3s/ch04
make
openFPGALoader --board ulx3s ch04.bit
For example, text mode (chapter 4) on ULX3S:
cd isle/boards/ulx3s/ch04
make
openFPGALoader --board ulx3s ch04.bit
December 13, 2025 at 12:22 PM
Isle is open hardware and uses an open-source toolchain (Yosys & nextpnr) for ECP5 #FPGA. With the toolchain installed, it's quick and simple to get Isle running.
For example, text mode (chapter 4) on ULX3S:
cd isle/boards/ulx3s/ch04
make
openFPGALoader --board ulx3s ch04.bit
For example, text mode (chapter 4) on ULX3S:
cd isle/boards/ulx3s/ch04
make
openFPGALoader --board ulx3s ch04.bit
The tools I've used so far are:
- Your favorite editor to write code
- make as a build system
- yosys for synthesis
- nextpnr for PnR (and bitstream generation)
- openFPGALoader to flash it to the FPGA
- verilator/Icarus Verilog for simulation
- gtkwave/Surfer for viewing waveforms
- Your favorite editor to write code
- make as a build system
- yosys for synthesis
- nextpnr for PnR (and bitstream generation)
- openFPGALoader to flash it to the FPGA
- verilator/Icarus Verilog for simulation
- gtkwave/Surfer for viewing waveforms
July 10, 2025 at 11:27 AM
The tools I've used so far are:
- Your favorite editor to write code
- make as a build system
- yosys for synthesis
- nextpnr for PnR (and bitstream generation)
- openFPGALoader to flash it to the FPGA
- verilator/Icarus Verilog for simulation
- gtkwave/Surfer for viewing waveforms
- Your favorite editor to write code
- make as a build system
- yosys for synthesis
- nextpnr for PnR (and bitstream generation)
- openFPGALoader to flash it to the FPGA
- verilator/Icarus Verilog for simulation
- gtkwave/Surfer for viewing waveforms
DirtyJtag is the first 3rd party firmware port to the Bus Pirate. It creates a JTAG cable compatible with UrJTAG, openFPGALoader, and other software. There is also the typical spare UART. Feedback is appreciated as I don't have many targets to test.
December 10, 2024 at 4:01 PM
DirtyJtag is the first 3rd party firmware port to the Bus Pirate. It creates a JTAG cable compatible with UrJTAG, openFPGALoader, and other software. There is also the typical spare UART. Feedback is appreciated as I don't have many targets to test.
If you have a Xilinx or Lattice JTAG dongle and you can find it, you should be able to use openFPGALoader instead. (Stuff like SignalTap etc won’t work though.)
December 9, 2024 at 9:25 PM
If you have a Xilinx or Lattice JTAG dongle and you can find it, you should be able to use openFPGALoader instead. (Stuff like SignalTap etc won’t work though.)
To program iCEBreaker after generating the SoC:
```
openfpgaloader -b ice40_generic build/icebreaker/gateware/icebreaker.bin
openfpgaloader -b ice40_generic -o 0x40000 build/icebreaker/software/bios/bios.bin
```
```
openfpgaloader -b ice40_generic build/icebreaker/gateware/icebreaker.bin
openfpgaloader -b ice40_generic -o 0x40000 build/icebreaker/software/bios/bios.bin
```
February 19, 2025 at 9:10 PM
To program iCEBreaker after generating the SoC:
```
openfpgaloader -b ice40_generic build/icebreaker/gateware/icebreaker.bin
openfpgaloader -b ice40_generic -o 0x40000 build/icebreaker/software/bios/bios.bin
```
```
openfpgaloader -b ice40_generic build/icebreaker/gateware/icebreaker.bin
openfpgaloader -b ice40_generic -o 0x40000 build/icebreaker/software/bios/bios.bin
```
I use openFPGALoader and a Xilinx dongle all the time to load Lattice ECP5 bitstreams. The official supported list of Altera FPGAs is limited, but chances are it will work.
December 9, 2024 at 9:57 PM
I use openFPGALoader and a Xilinx dongle all the time to load Lattice ECP5 bitstreams. The official supported list of Altera FPGAs is limited, but chances are it will work.
Vous couchez pas trop tard car demain matin 8h ça devient hard et on arrête de simuler. Au menu: #FPGA, #LiteX, ECP5, #RISC-V, rp2040, dirtyJTAG, openFPGAloader... et, si on a le temps et que j'arrive à me tenir, peut-être même du C.
Et ça se passe ici : www.twitch.tv/lefinnois_
Et ça se passe ici : www.twitch.tv/lefinnois_
Twitch
Twitch is the world
www.twitch.tv
March 21, 2026 at 5:31 PM
Vous couchez pas trop tard car demain matin 8h ça devient hard et on arrête de simuler. Au menu: #FPGA, #LiteX, ECP5, #RISC-V, rp2040, dirtyJTAG, openFPGAloader... et, si on a le temps et que j'arrive à me tenir, peut-être même du C.
Et ça se passe ici : www.twitch.tv/lefinnois_
Et ça se passe ici : www.twitch.tv/lefinnois_
openFPGALoaderのインストールに手間取った
September 19, 2026 at 3:26 AM
openFPGALoaderのインストールに手間取った
There are lots of excellent FPGA tools for Linux. OpenFPGALoader supports lots of devices. But raw JTAG will tell you a lot.
August 23, 2026 at 7:16 AM
There are lots of excellent FPGA tools for Linux. OpenFPGALoader supports lots of devices. But raw JTAG will tell you a lot.
Another day, another Altera MAX10 update! With OpenFPGALoader, you can now use the --flash-sector option to update one or more specific flash sectors instead of rewriting the entire internal flash.
March 18, 2025 at 9:49 PM
Another day, another Altera MAX10 update! With OpenFPGALoader, you can now use the --flash-sector option to update one or more specific flash sectors instead of rewriting the entire internal flash.
A logic analyser might help? I use pulseview which has a JTAG protocol analyser, so you can see if it is talking JTAG as expected. I've not used xc3sprog. I use OpenFPGALoader, not sure if that supports the Spartan 3. But JTAG is JTAG.
August 29, 2026 at 5:00 AM
A logic analyser might help? I use pulseview which has a JTAG protocol analyser, so you can see if it is talking JTAG as expected. I've not used xc3sprog. I use OpenFPGALoader, not sure if that supports the Spartan 3. But JTAG is JTAG.
Hardware in the Loop Continuous Integration for FPGA tools
http://pepijndevos.nl/2026/02/17/hardware-in-the-loop-continuous-integration-for-fpga-tools.html
#electronics #maker
http://pepijndevos.nl/2026/02/17/hardware-in-the-loop-continuous-integration-for-fpga-tools.html
#electronics #maker
Hardware in the Loop Continuous Integration for FPGA tools
Summary: Hardware in the Loop CI for FPGA tools using Raspberry Pi, Home Assistant, OpenFPGALoader, and UART verification
pepijndevos.nl
February 19, 2026 at 12:17 AM
Hardware in the Loop Continuous Integration for FPGA tools
http://pepijndevos.nl/2026/02/17/hardware-in-the-loop-continuous-integration-for-fpga-tools.html
#electronics #maker
http://pepijndevos.nl/2026/02/17/hardware-in-the-loop-continuous-integration-for-fpga-tools.html
#electronics #maker
As of today, I am claiming credit as the first Shure associate in the 101 year history of Shure Incorporated to officially contribute to an open source project by completing our new Open Source Contribution process!
Thank you Gwenhael Goavec-Merou for maintaining the excellent openFPGALoader […]
Thank you Gwenhael Goavec-Merou for maintaining the excellent openFPGALoader […]
Original post on mastodon.social
mastodon.social
July 13, 2026 at 9:02 PM
As of today, I am claiming credit as the first Shure associate in the 101 year history of Shure Incorporated to officially contribute to an open source project by completing our new Open Source Contribution process!
Thank you Gwenhael Goavec-Merou for maintaining the excellent openFPGALoader […]
Thank you Gwenhael Goavec-Merou for maintaining the excellent openFPGALoader […]
🎉 openFPGALoader v1.0.0 is out!
Major highlights:
• Complete spiOverJtag rework for Xilinx(complex chains)
• New Sponsors/Partners section
• AlteraFPGA MAX10
• Lattice ECP3 + ECP5's SSPI
• EspressifSystem ESP32-S3 as JTAG
🔗 github.com/trabucayre/o...
Thanks to all!
Major highlights:
• Complete spiOverJtag rework for Xilinx(complex chains)
• New Sponsors/Partners section
• AlteraFPGA MAX10
• Lattice ECP3 + ECP5's SSPI
• EspressifSystem ESP32-S3 as JTAG
🔗 github.com/trabucayre/o...
Thanks to all!
September 12, 2025 at 3:10 PM
🎉 openFPGALoader v1.0.0 is out!
Major highlights:
• Complete spiOverJtag rework for Xilinx(complex chains)
• New Sponsors/Partners section
• AlteraFPGA MAX10
• Lattice ECP3 + ECP5's SSPI
• EspressifSystem ESP32-S3 as JTAG
🔗 github.com/trabucayre/o...
Thanks to all!
Major highlights:
• Complete spiOverJtag rework for Xilinx(complex chains)
• New Sponsors/Partners section
• AlteraFPGA MAX10
• Lattice ECP3 + ECP5's SSPI
• EspressifSystem ESP32-S3 as JTAG
🔗 github.com/trabucayre/o...
Thanks to all!
Testé à l'instant avec l'esp32-s3 : openFPGALoader --fpga-part xc7k70tfbg676 --cable esp32s3 --detect -f
(pas oublier le --fpga-part).
(pas oublier le --fpga-part).
September 2, 2026 at 4:20 PM
Testé à l'instant avec l'esp32-s3 : openFPGALoader --fpga-part xc7k70tfbg676 --cable esp32s3 --detect -f
(pas oublier le --fpga-part).
(pas oublier le --fpga-part).
OMGGGG, first few steps of SD card initalization work!!! #this-one-probably-wins-the-price-of-the-worst-ever-state-machine-I-wrote #it's-basically-two-different-state-machines-frankensteined-together #VHDL #HDL #Icepi-Zero #FPGA
![╰─λ openFPGALoader --board icepi-zero build/top.bit && picocom /dev/ttyUSB0 -b 115200 -c --omap lfcrlf --imap spchex,tabhex,crhex,lfhex,nrmhex,8bithex
Jtag probe limited to 3MHz
Jtag frequency : requested 6000000Hz -> real 3000000Hz
ret 0
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
picocom v3.1
port is : /dev/ttyUSB0
flowcontrol : none
baudrate is : 115200
parity is : none
databits are : 8
stopbits are : 1
escape is : C-a
local echo is : yes
noinit is : no
noreset is : no
hangup is : no
nolock is : no
send_cmd is : sz -vv
receive_cmd is : rz -vv -E
imap is : spchex,tabhex,crhex,lfhex,8bithex,nrmhex,
omap is : lfcrlf,
emap is : crcrlf,delbs,
logfile is : none
initstring : none
exit_after is : not set
exit is : no
Type [C-a] [C-h] to see available commands](https://cdn.bsky.app/img/feed_thumbnail/plain/did:plc:k5kvpj3hu4l7qpqev274pzrw/bafkreiegnovxkbbj7rkbhj2clc3eccs5ckdyp2opr5b7rhmfv5sa7quoui)
August 22, 2026 at 3:25 AM
OMGGGG, first few steps of SD card initalization work!!! #this-one-probably-wins-the-price-of-the-worst-ever-state-machine-I-wrote #it's-basically-two-different-state-machines-frankensteined-together #VHDL #HDL #Icepi-Zero #FPGA
FPGA toolchains I've worked with in order from least to most painful (imo):
- GHDL + Yosys + nextpnr + openFPGALoader
- GOWIN EDA (didn't work much with it, but I like how lightweight it is)
- AMD/Xilinx Vivado
- Intel/Altera Quartus Prime (didn't work that much with it tho)
- Microc[...]
- GHDL + Yosys + nextpnr + openFPGALoader
- GOWIN EDA (didn't work much with it, but I like how lightweight it is)
- AMD/Xilinx Vivado
- Intel/Altera Quartus Prime (didn't work that much with it tho)
- Microc[...]
See complete post at wafrn.jcm.re
wafrn.jcm.re is a Wafrn server. Wafrn is a federated social media inspired by Tumblr, join us and have fun!
wafrn.jcm.re
August 9, 2026 at 9:32 PM
FPGA toolchains I've worked with in order from least to most painful (imo):
- GHDL + Yosys + nextpnr + openFPGALoader
- GOWIN EDA (didn't work much with it, but I like how lightweight it is)
- AMD/Xilinx Vivado
- Intel/Altera Quartus Prime (didn't work that much with it tho)
- Microc[...]
- GHDL + Yosys + nextpnr + openFPGALoader
- GOWIN EDA (didn't work much with it, but I like how lightweight it is)
- AMD/Xilinx Vivado
- Intel/Altera Quartus Prime (didn't work that much with it tho)
- Microc[...]
veryl+yosys+nextpnr+openFPGALoaderでLチカできた．
July 20, 2026 at 1:36 PM
veryl+yosys+nextpnr+openFPGALoaderでLチカできた．
検討中ボードのFPGA書き換えはOpenOCDを検討しているけどOpenFPGALoaderというのもあるらしい。
https://trabucayre.github.io/openFPGALoader/
https://trabucayre.github.io/openFPGALoader/
January 21, 2024 at 9:06 AM
検討中ボードのFPGA書き換えはOpenOCDを検討しているけどOpenFPGALoaderというのもあるらしい。
https://trabucayre.github.io/openFPGALoader/
https://trabucayre.github.io/openFPGALoader/
openFPGALoader 1.1.0 🎉
https://github.com/trabucayre/openFPGALoader/releases/tag/v1.1.0
https://github.com/trabucayre/openFPGALoader/releases/tag/v1.1.0
Release v1.1.0 release · trabucayre/openFPGALoader
Evolution summary: core new added option to select/deselect all cables, added variables ENABLE_xxx to enable corresponding cables. Some vendor drivers needs to to be disabled accordlingly CMakeLis...
github.com
March 1, 2026 at 12:51 PM
openFPGALoader 1.1.0 🎉
https://github.com/trabucayre/openFPGALoader/releases/tag/v1.1.0
https://github.com/trabucayre/openFPGALoader/releases/tag/v1.1.0
installing the latest yosys and openxc7 wasn't too bad, but I did have to fork two repos to make it work on Ubuntu 24.04. a simple LEDs-and-switches app works. next up: combined PS+PL deployments using GenZ, probably also messing around with DSP48E1 slices
![console output from programming a Zybo Z7-20 using openxc7:
Info: Running post-routing legalisation...
fasm2frames --part xc7z020clg400-1 --db-root /opt/openxc7/share/nextpnr/prjxray-db/zynq7 out/blinky2.fasm > out/blinky2.frames
xc7frames2bit --part_file /opt/openxc7/share/nextpnr/prjxray-db/zynq7/xc7z020clg400-1/part.yaml --part_name xc7z020clg400-1 --frm_file out/blinky2.frames --output_file out/blinky2.bit
openFPGALoader --board zybo_z7_20 --bitstream out/blinky2.bit
empty
Jtag frequency : requested 6.00MHz -> real 6.00MHz
Open file DONE
Parse file DONE
load program
Load SRAM: [===================================================] 100.00%
Done](https://cdn.bsky.app/img/feed_thumbnail/plain/did:plc:ncwcsl2uejt5ci5qgn7spgis/bafkreihymbvgfgqznzxxxqubudrw7bmjnamw6kx75cg2vfetyomkue5ztq)
May 25, 2026 at 6:33 PM
installing the latest yosys and openxc7 wasn't too bad, but I did have to fork two repos to make it work on Ubuntu 24.04. a simple LEDs-and-switches app works. next up: combined PS+PL deployments using GenZ, probably also messing around with DSP48E1 slices