I took inspiration from @mrjimmystones.bsky.social and built my own verilator-based simulator. This allows for significantly faster compile times, 10 seconds vs 13 minutes. It makes it possible to trace the entire state of the system at any time.
April 6, 2025 at 6:20 PM
I took inspiration from @mrjimmystones.bsky.social and built my own verilator-based simulator. This allows for significantly faster compile times, 10 seconds vs 13 minutes. It makes it possible to trace the entire state of the system at any time.
always fun when your compiler generates a program that causes another compiler to panic :) github.com/verilator/ve...
Internal error when handling typedefs containing parameterized class type members · Issue #7635 · verilator/verilator
The following module causes an internal fault during verilation (boiled down from the output of a compiler): class r#(parameter int W = 1); typedef struct packed { logic [W-1:0] unused; } t; endcla...
github.com
May 21, 2026 at 5:58 PM
always fun when your compiler generates a program that causes another compiler to panic :) github.com/verilator/ve...
Unicode UART goodness for 🏝️ Isle #FPGA Computer.
SDL key presses to UART via C++, sent to Isle hardware running under Verilator. The Isle #riscv asm software decodes the UTF-8 for display, including ▚ (U+259A).
We get Unicode user input in Verilator using same mechanism as physical dev boards. ☺️
SDL key presses to UART via C++, sent to Isle hardware running under Verilator. The Isle #riscv asm software decodes the UTF-8 for display, including ▚ (U+259A).
We get Unicode user input in Verilator using same mechanism as physical dev boards. ☺️
February 5, 2026 at 4:43 PM
Verilated MCGA brought up using Bochs with the IBM BIOS, generated from script-driven translations of @tubetime.bsky.social's schematic captures. Still buggy. Still fun.
May 19, 2026 at 3:40 PM
Verilated MCGA brought up using Bochs with the IBM BIOS, generated from script-driven translations of @tubetime.bsky.social's schematic captures. Still buggy. Still fun.
Isle computer supports machdyne Lakritz, Digilent Nexys Video, and Radiona #ULX3S.
And it's easy to run Isle's simulation; for example on macOS with brew installed:
brew install verilator sdl2
cd isle/boards/verilator/ch04
make
./obj_dir/ch04 # run sim
And it's easy to run Isle's simulation; for example on macOS with brew installed:
brew install verilator sdl2
cd isle/boards/verilator/ch04
make
./obj_dir/ch04 # run sim
December 13, 2025 at 10:11 AM
Isle computer supports machdyne Lakritz, Digilent Nexys Video, and Radiona #ULX3S.
And it's easy to run Isle's simulation; for example on macOS with brew installed:
brew install verilator sdl2
cd isle/boards/verilator/ch04
make
./obj_dir/ch04 # run sim
And it's easy to run Isle's simulation; for example on macOS with brew installed:
brew install verilator sdl2
cd isle/boards/verilator/ch04
make
./obj_dir/ch04 # run sim
Designing a font using only a few rects and triangles per glyph is satisfying if a little tedious. Another test for my #FPGA graphics engine and assets for future demos.
April 29, 2025 at 5:34 PM
Designing a font using only a few rects and triangles per glyph is satisfying if a little tedious. Another test for my #FPGA graphics engine and assets for future demos.
Working on an #FPGA demo for NOVA demoparty in June. Verilator/SDL simulation for quick turnaround when designing vector graphics. I think this year's wild compo will be epic.
May 15, 2025 at 6:05 PM
Working on an #FPGA demo for NOVA demoparty in June. Verilator/SDL simulation for quick turnaround when designing vector graphics. I think this year's wild compo will be epic.
Well, it works in simulation with one clock domain. But will 🏝️ Isle.Computer hardware registers work on real hardware with two clock domains? 🤔 #FPGA
June 2, 2026 at 9:55 PM
Well, it works in simulation with one clock domain. But will 🏝️ Isle.Computer hardware registers work on real hardware with two clock domains? 🤔 #FPGA
the mcga end-to-end simulator combines bochs and verilator with the ibm bios and injects boot sector code for the tests. but now I know how they detect a 15khz monitor to switch to a different mode table, so that's cool.
June 1, 2026 at 12:16 AM
the mcga end-to-end simulator combines bochs and verilator with the ibm bios and injects boot sector code for the tests. but now I know how they detect a 15khz monitor to switch to a different mode table, so that's cool.
Dan Guisselquist, le niveau de bigoterie crasse de ce type est effarante.
Et pourtant ses articles sur le développement FPGA sont très détaillé et hyper intéressant (Verilog, verilator, preuve formelle, ...).
Le lire c'est un peu comme lire des articles de Sam & Max sur python.
La religion ça […]
Et pourtant ses articles sur le développement FPGA sont très détaillé et hyper intéressant (Verilog, verilator, preuve formelle, ...).
Le lire c'est un peu comme lire des articles de Sam & Max sur python.
La religion ça […]
Original post on piaille.fr
piaille.fr
September 29, 2026 at 11:12 AM
Dan Guisselquist, le niveau de bigoterie crasse de ce type est effarante.
Et pourtant ses articles sur le développement FPGA sont très détaillé et hyper intéressant (Verilog, verilator, preuve formelle, ...).
Le lire c'est un peu comme lire des articles de Sam & Max sur python.
La religion ça […]
Et pourtant ses articles sur le développement FPGA sont très détaillé et hyper intéressant (Verilog, verilator, preuve formelle, ...).
Le lire c'est un peu comme lire des articles de Sam & Max sur python.
La religion ça […]
Verilator: open-source SystemVerilog simulator and lint system https://lobste.rs/s/k1zusu ##hardware
GitHub - verilator/verilator: Verilator open-source SystemVerilog simulator and lint system
Verilator open-source SystemVerilog simulator and lint system - verilator/verilator
github.com
March 20, 2026 at 8:40 PM
Verilator: open-source SystemVerilog simulator and lint system https://lobste.rs/s/k1zusu ##hardware
The #Verilog source for all four dev boards and Verilator simulation is available on GitHub under the MIT licence: github.com/projf/projf-...
December 27, 2024 at 5:37 PM
The #Verilog source for all four dev boards and Verilator simulation is available on GitHub under the MIT licence: github.com/projf/projf-...
this framebuffer is slowly being drawn by something under simulation (verilator + bochs) and in this case it's not my ip.
it belonged to number nine visual technology. this is the number nine "ticket to ride iv" vga/3d ip that was open sourced as "GPLGPU" - as exercised by bootloader code.
it belonged to number nine visual technology. this is the number nine "ticket to ride iv" vga/3d ip that was open sourced as "GPLGPU" - as exercised by bootloader code.
March 13, 2026 at 10:42 PM
this framebuffer is slowly being drawn by something under simulation (verilator + bochs) and in this case it's not my ip.
it belonged to number nine visual technology. this is the number nine "ticket to ride iv" vga/3d ip that was open sourced as "GPLGPU" - as exercised by bootloader code.
it belonged to number nine visual technology. this is the number nine "ticket to ride iv" vga/3d ip that was open sourced as "GPLGPU" - as exercised by bootloader code.
You can find the source code on GitHub (I'm considering moving to Codeberg): github.com/projf/isle
Includes everything you need for:
* Machdyne Lakritz (Lattice ECP5)
* @digilent.bsky.social Nexys Video (Xilinx XC7)
* Radiona #ULX3S (ECP5)
* Verilator simulator with SDL (Linux/macOS/Windows)
Includes everything you need for:
* Machdyne Lakritz (Lattice ECP5)
* @digilent.bsky.social Nexys Video (Xilinx XC7)
* Radiona #ULX3S (ECP5)
* Verilator simulator with SDL (Linux/macOS/Windows)
March 20, 2026 at 7:35 PM
You can find the source code on GitHub (I'm considering moving to Codeberg): github.com/projf/isle
Includes everything you need for:
* Machdyne Lakritz (Lattice ECP5)
* @digilent.bsky.social Nexys Video (Xilinx XC7)
* Radiona #ULX3S (ECP5)
* Verilator simulator with SDL (Linux/macOS/Windows)
Includes everything you need for:
* Machdyne Lakritz (Lattice ECP5)
* @digilent.bsky.social Nexys Video (Xilinx XC7)
* Radiona #ULX3S (ECP5)
* Verilator simulator with SDL (Linux/macOS/Windows)
@willflux.bsky.social Thanks to your FPGA & Verilator tutorial that provide valuable material for me to start doing graphics hardware.
ProjectF site and Steven Hugg’s book are absolute gems.
ProjectF site and Steven Hugg’s book are absolute gems.
May 9, 2026 at 1:35 AM
@willflux.bsky.social Thanks to your FPGA & Verilator tutorial that provide valuable material for me to start doing graphics hardware.
ProjectF site and Steven Hugg’s book are absolute gems.
ProjectF site and Steven Hugg’s book are absolute gems.
Over the weekend I worked on 🏝️Isle.Computer designs for chapter 6. I've now added the designs to a branch and you can already run the sim on your PC (Linux/Mac/Windows): github.com/projf/isle/t...
Please have a quick play and let me know how you get on. 🛝
Please have a quick play and let me know how you get on. 🛝
March 2, 2026 at 10:19 PM
Over the weekend I worked on 🏝️Isle.Computer designs for chapter 6. I've now added the designs to a branch and you can already run the sim on your PC (Linux/Mac/Windows): github.com/projf/isle/t...
Please have a quick play and let me know how you get on. 🛝
Please have a quick play and let me know how you get on. 🛝
The tools I've used so far are:
- Your favorite editor to write code
- make as a build system
- yosys for synthesis
- nextpnr for PnR (and bitstream generation)
- openFPGALoader to flash it to the FPGA
- verilator/Icarus Verilog for simulation
- gtkwave/Surfer for viewing waveforms
- Your favorite editor to write code
- make as a build system
- yosys for synthesis
- nextpnr for PnR (and bitstream generation)
- openFPGALoader to flash it to the FPGA
- verilator/Icarus Verilog for simulation
- gtkwave/Surfer for viewing waveforms
July 10, 2025 at 11:27 AM
The tools I've used so far are:
- Your favorite editor to write code
- make as a build system
- yosys for synthesis
- nextpnr for PnR (and bitstream generation)
- openFPGALoader to flash it to the FPGA
- verilator/Icarus Verilog for simulation
- gtkwave/Surfer for viewing waveforms
- Your favorite editor to write code
- make as a build system
- yosys for synthesis
- nextpnr for PnR (and bitstream generation)
- openFPGALoader to flash it to the FPGA
- verilator/Icarus Verilog for simulation
- gtkwave/Surfer for viewing waveforms
Isle targets Machdyne Lakritz, @digilent.bsky.social Nexys Video, Radiona ULX3S, and Verilator/SDL simulation that runs on your PC or Mac.
Designs, docs, and test benches are available under the MIT license: github.com/projf/isle
Designs, docs, and test benches are available under the MIT license: github.com/projf/isle
GitHub - projf/isle: Isle FPGA Computer
Isle FPGA Computer. Contribute to projf/isle development by creating an account on GitHub.
github.com
August 4, 2025 at 8:26 AM
Isle targets Machdyne Lakritz, @digilent.bsky.social Nexys Video, Radiona ULX3S, and Verilator/SDL simulation that runs on your PC or Mac.
Designs, docs, and test benches are available under the MIT license: github.com/projf/isle
Designs, docs, and test benches are available under the MIT license: github.com/projf/isle
I don't yet have a complete system to share with you. Getting the design right takes a lot of experimentation; I've hit dead ends several times. I'll gradually introduce components over the coming months. The first part looks at display signals. #FPGA 📺 projectf.io/isle/display...
August 4, 2025 at 9:53 AM
I don't yet have a complete system to share with you. Getting the design right takes a lot of experimentation; I've hit dead ends several times. I'll gradually introduce components over the coming months. The first part looks at display signals. #FPGA 📺 projectf.io/isle/display...
Looks like I've found a real hardware rendering bug. I've only tested this in Verilator/SDL sim so far, but time for me for me to call it a night. I can check it on FPGA when I'm back at my desk. 😴
August 16, 2026 at 12:04 AM
Looks like I've found a real hardware rendering bug. I've only tested this in Verilator/SDL sim so far, but time for me for me to call it a night. I can check it on FPGA when I'm back at my desk. 😴