Bank 1 connects directly to gigabit transceivers, those can't be used as GPIO.
Banks 2 and 3 connect to standard FPGA I/O, some of which could be configured to be differential across paired pins.
I am using banks 2+3 as level-shifted standard I/O, and speaking ISA bus.
Bank 1 connects directly to gigabit transceivers, those can't be used as GPIO.
Banks 2 and 3 connect to standard FPGA I/O, some of which could be configured to be differential across paired pins.
I am using banks 2+3 as level-shifted standard I/O, and speaking ISA bus.
bsky.app/profile/fura...
bsky.app/profile/fura...