#AdvancedPackaging
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qmshahzad.bsky.social
Advanced packaging is emerging as a critical constraint as Nvidia, AMD and other companies race to supply AI chips. #Semiconductors #AIChips #AdvancedPackaging
Chip Packaging Becomes AI’s Next Bottleneck
November 7, 2026 at 5:46 AM
edsonbellido.bsky.social
2/4 Mechanism: wafer-to-wafer bonding cuts data travel from millimeters to micrometers. Claims: 18x effective bandwidth over LPDDR5X, 5x+ bandwidth per watt vs projected HBM4. Slightly below their own 6x efficiency projection. #Chips #AdvancedPackaging
November 6, 2026 at 1:30 PM
chipress.bsky.social
The Chiplet Shift: From Silicon Scaling to Packaging Innovation in AI Accelerators chipress.online/2026/11/08/t...

#AdvancedPackaging #Chiplets #AI #CoWoS #SoIC #TSMC
The Chiplet Shift: Beyond Monoliths for AI Accelerator Scaling
Why break monolithic dies? Explore chiplet pivot, 2D/3D integration trade-offs (CoWoS, SoIC), thermal constraints, and how AMD MI300 series combines both
chipress.online
November 8, 2026 at 11:56 PM
eetimes.bsky.social
AI Hardware’s Hidden Cost: Between Orders and Output

Why is #AI hardware piling up? Alphabet, Intel, Lam, and KLA filings show substrates, packaging, and power delay returns on capital. #AdvancedPackaging #SupplyChain...

https://www.eetimes.com/ai-hardwares-hidden-cost-between-orders-and-output/
AI Hardware’s Hidden Cost: Between Orders and Output
Why is #AI hardware piling up? Alphabet, Intel, Lam, and KLA filings show substrates, packaging, and power delay returns on capital. #AdvancedPackaging #SupplyChain
www.eetimes.com
November 3, 2026 at 2:09 PM
vlsikorea.bsky.social
Nvidia prepaid $3B to Amkor and $1.1B to KYEC just to reserve packaging and test capacity.

I build chips in Seoul: a prepayment is demand conviction you can audit.

If capacity is the constraint, who holds pricing power?

#Semiconductor #AdvancedPackaging
Intel fab cleanroom with EUV lithography equipment, illustrating the capacity race behind supplier prepayments
November 4, 2026 at 2:17 PM
jissonews.bsky.social
11月19日(木)13:00-16:30に、日本実装技術振興協会 #JJTTA が第241回定例講演会『トレンドにおける実装技術の今を探る』を開催。川崎市幸区・川崎市産業振興会館およびオンラインにて。講演3件と会社紹介1件。講演後に技術交流会。詳細は www.j-jisso.org/pdf/... に。
#Seminar #LiquidCooling #Reflow #AdvancedPackaging
November 4, 2026 at 11:50 PM
thestartupmac.com
The AI Boom Is Triggering a New Semiconductor Battle. #artificialintelligence #airevolution #semiconductors #nvidia #amd #chiptechnology #advancedpackaging #aichips #technews #technologynews
The next big battle in Artificial Intelligence may not be about AI models. It could be about the chips that power them. As demand for AI computing continues to surge, NVIDIA, AMD and other semiconductor companies are racing to secure advanced chip-packaging capacity. Why does this matter? 🔹 Rising AI Demand: Powerful AI models require increasingly advanced processors. 🔹 Advanced Packaging: Technologies such as CoWoS and 3D chip stacking are becoming critical to improving chip performance. 🔹 Supply Chain Competition: Access to advanced manufacturing and packaging capacity is becoming a major competitive advantage. 🔹 Industry Expansion: Semiconductor manufacturers are investing in new capabilities to meet growing demand. The bigger picture: The semiconductor industry is entering a new phase of competition. Building powerful AI chips is important, but packaging them efficiently at scale is becoming equally critical. The future of AI will depend not only on smarter software but also on stronger semiconductor infrastructure.
November 6, 2026 at 8:00 AM
edsonbellido.bsky.social
4/4 Source: Semiconductor Digest, by Anand Murthy. Full report: https://www.semiconductor-digest.com/lam-and-imec-expand-collaboration-to-advance-manufacturability-of-next-gen-3d-integration-technologies/ #Semiconductors #AdvancedPackaging
November 2, 2026 at 1:30 AM
edsonbellido.bsky.social
2/4 The split: Lam supplies deep deposition and etch, imec supplies integration infrastructure plus its high NA EUV lab. Joint targets: thick dielectric deposition, bevel deposition, plasma dicing, high aspect ratio channel etch for 3D memory. #Chips #AdvancedPackaging
November 2, 2026 at 1:30 AM
edsonbellido.bsky.social
1/4 Transistor scaling alone no longer delivers AI compute gains. The hard part is making 3D integration manufacturable at volume, and Lam and imec just expanded their alliance to attack that gap. 🧵 #Semiconductors #AdvancedPackaging
SemiRecap Infographic [STRATEGIC_PARTNERSHIP_MOU]: Lam and imec Expand 3D Integration Collaboration. A stylized 2.5D vector cartoon illustration on solid white background (#FFFFFF) showing a deep maroon Lam process module labeled 'LAM: DEPOSITION & ETCH' docked into an imec cleanroom integration bay labeled 'IMEC: INTEGRATION INFRASTRUCTURE', with a robotic arm passing a 3D stacked wafer across the partner interface over cyan bus traces. A second vignette shows the Aether dry resist module feeding a high NA EUV scanner whose beam patterns gold ruthenium interconnect lines on a wafer labeled 'SUB 20NM RU DME' with yield badges '100% FORK' and '>90% MEANDER', connected by amber gold traces to a roadmap flag marked 'GAA / CFET'.
November 2, 2026 at 1:30 AM
edsonbellido.bsky.social
4/4 Source: Terafab's Single Roof by Shaurya Seth, SemiWiki. 🔗 https://semiwiki.com/semiconductor-manufacturers/374838-terafabs-single-roof-why-packaging-not-lithography-decides-high-volume/ #AdvancedPackaging #HBM
October 18, 2026 at 12:30 PM
edsonbellido.bsky.social
1/4 Terafab's $16.8B bet: logic, memory and packaging under one roof. The roof fixes logistics, not the physics inside the joint. Packaging, not lithography, decides whether high volume pays off. 🧵 #Semiconductors #AdvancedPackaging
SemiRecap Infographic [HARDWARE_DEEP_DIVE]: Terafab's Single Roof: Packaging Decides High Volume. A clean 2.5D vector cartoon tech illustration on a solid pure white background (#FFFFFF). A single roof fab building labeled TERAFAB spans two wings: AUSTIN RESEARCH FAB and GRIMES COUNTY FAB 100K WSPM. Inside, a Deep Maroon logic die sits beside a 16 HIGH HBM STACK with warm gold pins and cyan bus traces. A magnified inset shows the joint evolution: CU PILLAR + SNAG CAP at 20 µm PITCH with one joint flagged BRIDGE RISK, transitioning to a SOLDERLESS HYBRID BOND copper interface. Adjacent, a CMP + ACTIVATION MODULE carries a Q TIME LIMIT timer badge. A phased arrow runs from an INTEL EMIB block to 2.5D IN HOUSE to HYBRID BONDING, ending at a NANOTWINNED CU 200°C badge. Deep Maroon (#450d16) primary chip color, warm gold pins, cyan bus traces.
October 18, 2026 at 12:30 PM
jissonews.bsky.social
2027年1月22日(金)13:00〜17:30に、アジア半導体機構 #ASTSA が「デバイス実装研究会」を開催。九州経済調査協会などが共催。講演5件。超集積実装、大型ガラスパネル基板、新開発の仮固定材、リンテックの新材料と糸島で始動する研究所、超厚膜熱酸化膜。福岡市中央区・ホテルニューオータニ博多およびオンライン(Zoom)にて。詳細は https://x.gd/txN0T に。PDF版案内は https://x.gd/3g9xk に。
#Seminar #AdvancedPackaging #GlassSubstrate #Kyushu
October 15, 2026 at 4:15 AM
edsonbellido.bsky.social
4/4 Source: 2.5D vs 3D Packaging: What Is the Difference? by AnySilicon. Full article: https://anysilicon.com/2-5d-vs-3d-packaging-what-is-the-difference/ #Semiconductors #AdvancedPackaging
October 14, 2026 at 12:30 PM
edsonbellido.bsky.social
4/4 Source: Semiconductor Digest — https://www.semiconductor-digest.com/globalfoundries-tsmc-agreement-for-u-s-ai-chip-packaging-components/ #Semiconductors #AdvancedPackaging #CoWoS
October 14, 2026 at 12:30 AM
edsonbellido.bsky.social
2/4 GF adds fabrication capacity at Malta to supply interposers with embedded deep trench capacitor components. Volume production is expected to begin ramping in H1 2028. Initial term: five years, with a framework for capacity expansion. #AdvancedPackaging #Chips
October 14, 2026 at 12:30 AM
iwpost.bsky.social
The Frontier Express: when Samsung gets money#advancedpackaging #Block2 #logicchips #memorychips #SamsungElectronics #Technology
The Frontier Express: when Samsung gets money
For most of the past thirty years, the semiconductor industry ran on a remarkably clean division of labor. Everybody knew their place. The caricature was almost this simple: TSMC printed. Memory makers crammed capacitors. Designers drew. And the money followed the drawing. TSMC took designs from Nvi
iwpost.com
October 14, 2026 at 7:00 AM
jissonews.bsky.social
9月29日(火)に、Global Electronics Association（旧IPC）がドイツの研究機関 Fraunhofer Group for Microelectronics とMoU（覚書）を締結。 目的は、先端パッケージング技術を産業として普及させること。対象は、EU Chips Act（欧州半導体法）に基づく先端パッケージング・異種統合の欧州パイロットライン #APECS で、Fraunhofer-Gesellschaftが取りまとめる。→
#AdvancedPackaging #Chiplet #Fraunhofer
October 14, 2026 at 4:20 AM
edsonbellido.bsky.social
1/4 🧵 Every AI package hides a fork: dies beside each other on an interposer, or stacked vertically through hybrid bonding. 2.5D still carries AI and HPC volume, but 3D density keeps climbing. In 2026 the answer is increasingly both. #AdvancedPackaging #Semiconductors
SemiRecap Infographic [HARDWARE_DEEP_DIVE]: 2.5D vs 3D Packaging: Key Differences Explained. A clean 2.5D vector cartoon tech illustration on solid pure white background (#FFFFFF). Left panel shows a 2.5D package: a Deep Maroon (#450d16) compute die and two HBM stacks placed side by side on a labeled 'SILICON INTERPOSER' with cyan bus traces fanning between the dies, all seated on a 'PACKAGE SUBSTRATE' with warm gold pins. Right panel shows a 3D stack: two Deep Maroon dies vertically bonded, with a cutaway revealing gold 'TSV' pillars and a 'HYBRID BOND <10µm' interface line, labeled 'STACKED LOGIC' and 'BASE DIE'. A center arrow labeled '3.5D' merges both panels into one package combining vertically stacked memory above side-by-side chiplets on the interposer. Minimal clean structural labels identify each specific component.
October 14, 2026 at 12:30 PM
edsonbellido.bsky.social
4/4 📄 Source: THE ELEC, October 1, 2026. The EPIC Center is in final preparations, with R&D equipment moving into clean rooms and an unveiling ceremony set for October 12, 2026. #Chips #AdvancedPackaging
October 12, 2026 at 12:30 AM
edsonbellido.bsky.social
1/4 🧩 Advanced packaging is no longer simple back end assembly. Applied Materials and Besi are expanding their collaboration at the $5B EPIC Center in Silicon Valley, jointly developing D2W hybrid bonding, TCB, DoW, DoD, DoP and CPO. #Semiconductors #AdvancedPackaging
SemiRecap Infographic [STRATEGIC_PARTNERSHIP_MOU]: Applied Materials and Besi Deepen Hybrid Bonding Alliance. A 2.5D vector cartoon illustration on solid white background (#FFFFFF) showing two large modular equipment blocks docking inside an EPIC Center cleanroom: a Deep Maroon (#450d16) Applied Materials process module labeled with etch, deposition and metrology icons, and a Besi assembly module with die placement arms. Their interface is a glowing cyan hybrid bond chamber where a die is bonded directly onto a wafer with copper pads, no solder bumps shown. A gold process flow arrow runs from WLP to PLP panel stages, with a small CPO optical interconnect chip glowing at the end.
October 12, 2026 at 12:30 AM
edsonbellido.bsky.social
2/4 Scope: joint process and equipment R&D across FEOL, BEOL, and packaging. Targets: higher interconnect density, better power delivery, thermal headroom for agentic AI HPC. Plus new logic materials and Foveros 3D stacking. #Chips #AdvancedPackaging
October 9, 2026 at 12:30 AM
mengli512.bsky.social
Is Teradyne stock a sustainable long-term investment, or does the recent revenue guidance drop signal trouble for the company?

#ai #testing #robotics #optical #chip #memory #advancedpackaging #$TER #$ROK #$ZBRA
youtu.be/m7ytk0_1-SU
Teradyne: Is the AI Gold Rush Over for Testing?
YouTube video by Meng Li
youtu.be
October 2, 2026 at 7:52 AM
edsonbellido.bsky.social
Full capacity arrives by 2029 at about 44,000 wafers per month with 1,600 jobs. For NXP this is automotive and industrial supply security. For the industry, more 300mm capacity where analog flows meet interposer demand. #AutomotiveChips #AdvancedPackaging
October 1, 2026 at 9:00 PM
edsonbellido.bsky.social
Memory bandwidth and system in package architectures are evolving rapidly. Projections show 2029 memory benchmarks increasing drastically, with HBM bandwidth scaling 34x and 3D DRAM jumping 115x. #Semiconductors #AdvancedPackaging
September 30, 2026 at 7:00 PM