Chiplet IC Market was valued at USD 4.8 billion in 2025 and is expected to reach USD 13.1 billion by 2034, exhibiting a CAGR of 10.7%

Why break monolithic dies? Explore chiplet pivot, 2D/3D integration trade-offs (CoWoS, SoIC), thermal constraints, and how AMD MI300 series combines both

Chiplet interconnect UCIe physical-layer jitter budget market reached USD 460 million in 2025 and is forecast at USD 790 million in 2034, representing 6.2% CAGR in the 2026–2034

Chiplet market reached USD 1,850 million in 2025 and is expected to attain USD 8,000 million by 2034, representing 17.7% CAGR in the 2026–2034

Chiplet UCIe retimer for die-to-die clock forwarding market was valued at USD 450 million in 2025 and is expected to reach USD 1,120 million by 2034, reflecting a CAGR of 10.7% across 2026–2034.

AMD gaat met zijn nieuwe Zen 6-architectuur de grootste stap in jaren zetten. De cores worden niet alleen sneller, maar ook de aantallen gaan omhoog.

Chiplet packaging technology sits at the intersection of heterogeneous integration, advanced packaging, and semiconductor supply-chain resilience. The market size was valued at 1.

Chiplet-based Arm Neoverse server CPU for cloud-native market was valued at USD 1,850 million in 2025 and is projected to reach USD 3,420 million by 2034, with a CAGR of 7.1% during 2026–2034.

The transition to chiplet-based architectures has introduced complex electromagnetic hurdles that traditional, isolated design methods cannot resolve.

Silicon Box avvia il Vulcan Project a Novara: maxinvestimento da 3,2 miliardi per il packaging avanzato dei microchip e 1.600 posti di lavoro

YouTube video by Semiconductor Engineering

$86,009,965. That is the exact sum PowerLattice Technologies reported selling in a Form D equity offering filed on October 30, 2026 — toward a $111,010,000 target, from 18 accredited investors, for a chip that performs no arithmetic. The chiplet's only job is to take the electricity that reaches an AI accelerator and drop it to the voltage the processor needs, a few millimetres from the transistors that consume it. PowerLattice says moving regulation inside the package cuts total compute power demand by more than half and can double throughput under a fixed power budget. Those are company claims, not independently measured results. The timing of the raise still tells you what the market believes: the binding constraint on AI infrastructure has moved from the processor to the wire, the board and the package that feeds it. If that thesis holds, the next valuable AI hardware franchise may not build logic at all. It may own the last millimetre of power delivery. 🎯 **The $86M filing is a hardtech bet on packaging, not compute.** AI accelerators now exceed 2,000W per chip, and point-of-load delivery overhead grows faster than useful compute as current rises. PowerLattice claims more than 50% lower total compute power and up to 2x performance per watt; the figures come from its own load emulator, with no named customer or processor partner. The strategic read is consolidation: Analog Devices agreed in 2026 to buy Empower Semiconductor for $1.5B, which prices on-package power delivery as an acquisition target. ## The Last Millimetre Became the Bottleneck An AI accelerator is a low-voltage, high-current device. At roughly 0.7V and 1,000A, the current path matters as much as the transistor. Power drawn at the package edge must travel through board traces, socket pins and package routing before it reaches the compute die. Every millimetre of that path adds resistance and inductance, and both turn into heat. PowerLattice's own technical figures put the overhead in perspective. At a 700W accelerator, the company estimates 476W of delivery overhead. At 1,800W, it puts overhead at 1,868W. At 3,500W — the direction high-end parts are heading — overhead reaches 4,845W. The numbers are vendor estimates, but the direction is not disputed: delivery loss grows faster than useful compute as current rises. The operational consequence is that accelerator utilisation gets throttled by power integrity, not by the arithmetic units. That is why power delivery has moved from a board-level concern to a package-level one, and why a small fabless company can argue it owns a strategic layer of the AI stack. ## What PowerLattice Actually Built The product is an integrated voltage regulator built as a chiplet and placed inside the processor package. The monolithic design puts the controller, the power transistors and the inductors on one piece of silicon. Its PowerMagix process integrates magnetic-film inductors on the die; its Programmable Power Array, P²A, lets multiple chiplets synchronise and behave as one larger regulator. The company calls the architecture Rainier. On October 26, 2026, PowerLattice demonstrated the chiplet under what it calls next-generation accelerator loads. The test powered a high-precision silicon device that PowerLattice built to emulate rapid current swings. It did not use a customer's processor. PowerLattice says the design can cut total compute power needs by more than 50%, deliver 2x or more raw performance under a fixed power budget, and reduce power noise by an order of magnitude. None of those figures has been independently verified. $86M Form D equity sold #### PowerLattice's reported raise $86,009,965 of a $111,010,000 offering, 18 accredited investors · _SEC Form D, October 2026_ ## The Filing: $86M of a $111M Target The Form D is a new notice, not an amendment. It reports a first sale on October 15, 2026, and was signed by chief executive Peng Zou on October 30. The securities are equity sold under Rule 506(b); the 18 investors are described as accredited, and none is named. The company declined to comment to GeekWire. Form D item| Figure ---|--- Total offering| $111,010,000 Amount sold| $86,009,965 Remaining to be sold| $25,000,035 Investors| 18 accredited First sale| October 15, 2026 Filing signed| October 30, 2026 Exemption| Rule 506(b) Source: SEC Form D for Powerlattice Technologies Inc, filed October 30, 2026. The raise is roughly 2.8x the $31 million PowerLattice had disclosed when it came out of stealth in November 2025, a total that included a $25 million Series A co-led by Playground Global and Celesta Capital. The filing does not label the new round, name the investors or describe use of proceeds. It lists Zou, Sujith Dermal and Gang Ren as officers and directors, alongside Steve Fu of Celesta, Pat Gelsinger of Playground and Wen Hsieh of Matter Venture Partners. ## Why the Package Beats the Grid on Timing Most of the capital chasing AI's power problem is aimed at generation, transmission and cooling. Those projects are measured in years and gated by interconnection queues. An on-package regulator is measured in quarters and ships inside every accelerator that adopts it. That difference in clock speed is the investment case. A grid solution adds capacity once, at a single site. A package-level efficiency gain compounds across an entire installed fleet, because each new accelerator carries it by default. If PowerLattice's claimed efficiency holds even partially, the addressable value is the difference between building more megawatts and getting more tokens from the megawatts already energised. ## A Hot Sector With a Consolidation Bid Power delivery has become an acquisition market. Analog Devices agreed in May 2026 to buy Empower Semiconductor for $1.5 billion, after Empower raised $140 million in 2025. That transaction gives private investors a benchmark for what a credible on-package power franchise is worth, and it gives PowerLattice a strategic exit path that did not exist two years ago. The board is part of the signal. Gelsinger, the former Intel chief executive, joined with the Series A and has framed the problem in the language the sector now uses. > AI is not constrained by capital, it's constrained by power.— Pat Gelsinger, former Intel CEO and PowerLattice board member, when the Series A was announced Gelsinger's presence does not validate the technology. It does indicate which incumbent customer conversations PowerLattice is likely to have, and why the company can raise at a premium before naming a production partner. ## What the Filing Does Not Say Three gaps matter for valuation. First, the demonstration used a PowerLattice-built load emulator. A customer processor with real thermal, packaging and firmware constraints is a harder test, and no qualification result has been published. Second, no production customer, processor partner or design win is disclosed. Without one, the $111 million target is a claim on future adoption, not evidence of it. Third, the filing gives no revenue range, no margin structure and no use of proceeds, so investors cannot tell whether the money buys tape-out, customer engineering or working capital. The margin question decides the outcome. If PowerLattice becomes a component supplier to accelerator vendors, it inherits the capital intensity and pricing pressure of the semiconductor supply chain. The company is fabless, which helps, but on-package power delivery requires close co-design with each customer. That work is expensive and slow. As we wrote in our October piece on the AI data center refresh trap, the operators capturing value are the ones who control the full stack, not the ones selling a single line item into it. ## Three Ways This Plays Out The forecast below is a scenario map, not a prediction of any single quarter. It assumes PowerLattice converts part of the $86 million into customer co-design work and that at least one accelerator vendor treats on-package regulation as a roadmap requirement rather than a science project. 🔮 **By the end of 2027, at least one top-five AI accelerator vendor will qualify an external on-package IVR for a production part.** Probability: 45% — the physics is real, the ADI–Empower deal set a price umbrella, and the capital is now in place. The binding unknown is customer qualification, not design. #### 🟢 Optimistic scenario (45%) A major GPU or custom-ASIC vendor qualifies the chiplet, and PowerLattice moves from samples to volume. The company becomes a strategic supplier with pricing power and an acquisition premium above the Empower benchmark. **Consequence:** the $86 million looks cheap relative to the resulting franchise. #### 🟡 Base scenario (35%) PowerLattice lands design engagements but not a flagship production socket before 2028. The technology is validated in engineering samples; the revenue case stays thin, and the next round prices on optionality rather than traction. **Consequence:** a good technology with a slow commercial clock. #### 🔴 Pessimistic scenario (20%) Independent testing narrows the efficiency gain, or incumbents bundle a competitive regulator into reference designs. PowerLattice's differentiation compresses and the company becomes an acquisition target at a modest multiple. **Consequence:** capital returned through consolidation, not scale. ## What to Watch 📊 **Signals that would change the thesis** A named processor partner or design win with a top-five accelerator vendor. Independent measurement of efficiency and transient response on a customer part. A follow-on round priced above the current offering, or an acquisition approach. Disclosure of revenue, margin or use of proceeds in a later Form D amendment. For now, the $86 million is best read as a priced option on a real engineering problem. The problem is not whether AI needs more power. It is whether the cheapest incremental token comes from building another gigawatt or from losing less of the gigawatt already installed. PowerLattice is betting on the second, and the filing shows that at least 18 accredited investors agreed closely enough to fund the attempt. SEC Form D — Powerlattice Technologies Inc The primary disclosure behind the $86M figure: offering size, amount sold, investor count, first-sale date and signatories. U.S. Securities and Exchange Commission Primary source. Every funding number in this piece traces back to this filing. Powerlattice demonstrates the industry's first monolithic IVR chiplet The October 26 technical announcement: architecture, PowerMagix inductors, P²A synchronisation and the company's efficiency claims. Powerlattice Company release. Useful for the technical detail, but the performance figures are self-reported. Filing: Chip startup Powerlattice raises $86M to ease AI's power crunch GeekWire's report on the Form D, the prior $31M total and the board composition, including Pat Gelsinger. GeekWire The clearest independent summary of what the filing does and does not disclose. PowerLattice raises $86M to break AI's power wall Dealroom's analysis of the round, the unverified savings claim and the ADI–Empower consolidation benchmark. Dealroom Best short treatment of the strategic context and the validation gap. PowerLattice demos monolithic IVR chiplet for AI accelerators A technical read on the demonstration, with a clear list of what was not disclosed: current, efficiency, thermals and process. Converge Digest Helpful for separating demonstrated facts from company claims.

ERS electronic has launched a fully automated 310×310 mm panel-level packaging system that integrates temporary carrier bonding, debonding and adhesive removal for AI and Chiplet packaging. The first unit was delivered in September to a well-known semiconductor manufacturer and integrated into its production line.

XPU unified processor market is valued at USD 8.10 billion in 2025 and is projected to reach USD 35.90 billion by 2034, expanding at a 18.1% CAGR

Kurt Schlosser / GeekWire: Filing: Vancouver, WA-based Powerlattice, which makes a power delivery chiplet to reduce AI compute power needs by 50%+, raised $86M, after raising $31M in 2025  —  Powerlattice, a Vancouver, Wash.-based startup developing chips that cut the power demands of AI processors, has raised $86 million, according to an SEC filing on Friday.

Kurt Schlosser / GeekWire: **Filing: Vancouver, WA-based Powerlattice, which makes a power delivery chiplet to reduce AI compute power needs by 50%+, raised $86M, after raising $31M in 2025** — Powerlattice, a Vancouver, Wash.-based startup developing chips that cut the power demands of AI processors, has raised $86 million, according to an SEC filing on Friday.