Chip of the Week: Masterpiece Byte Register and ALU!
A very rare sight: 4 purple metrics to get the elusive Masterpiece grade! Almost impossible to get.
This piece stores bytes in registers and crunches them with an ALU, the heart of a simple CPU.
#cpudesign #gamedev #Engineering #logic #puzzle
A very rare sight: 4 purple metrics to get the elusive Masterpiece grade! Almost impossible to get.
This piece stores bytes in registers and crunches them with an ALU, the heart of a simple CPU.
#cpudesign #gamedev #Engineering #logic #puzzle
November 9, 2026 at 8:20 PM
Chip of the Week: Masterpiece Byte Register and ALU!
A very rare sight: 4 purple metrics to get the elusive Masterpiece grade! Almost impossible to get.
This piece stores bytes in registers and crunches them with an ALU, the heart of a simple CPU.
#cpudesign #gamedev #Engineering #logic #puzzle
A very rare sight: 4 purple metrics to get the elusive Masterpiece grade! Almost impossible to get.
This piece stores bytes in registers and crunches them with an ALU, the heart of a simple CPU.
#cpudesign #gamedev #Engineering #logic #puzzle
Chip of the Week: The Tidy General Purpose Byte Register!
With the recent release of Chapter 2 in EA, some new stages mean new screenshots!
#cpudesign #gamedev #Engineering #logic #puzzle
With the recent release of Chapter 2 in EA, some new stages mean new screenshots!
#cpudesign #gamedev #Engineering #logic #puzzle
October 26, 2026 at 10:07 PM
Chip of the Week: The Tidy General Purpose Byte Register!
With the recent release of Chapter 2 in EA, some new stages mean new screenshots!
#cpudesign #gamedev #Engineering #logic #puzzle
With the recent release of Chapter 2 in EA, some new stages mean new screenshots!
#cpudesign #gamedev #Engineering #logic #puzzle
Chip of the Week: The Tigh 4Bytes Memory Bank
Not recent and still at the top of the charts! From one of the more intensely engaging stages. An agile grid row-select pattern!
#cpudesign #gamedev #Engineering #logic #puzzle
Not recent and still at the top of the charts! From one of the more intensely engaging stages. An agile grid row-select pattern!
#cpudesign #gamedev #Engineering #logic #puzzle
October 12, 2026 at 9:18 PM
Chip of the Week: The Tigh 4Bytes Memory Bank
Not recent and still at the top of the charts! From one of the more intensely engaging stages. An agile grid row-select pattern!
#cpudesign #gamedev #Engineering #logic #puzzle
Not recent and still at the top of the charts! From one of the more intensely engaging stages. An agile grid row-select pattern!
#cpudesign #gamedev #Engineering #logic #puzzle
Intel Patents CPU Package with Integrated MicroLEDs
#Intel #MicroLED #Semiconductor #CPUDesign #TechInnovation
#Intel #MicroLED #Semiconductor #CPUDesign #TechInnovation
Intel Patents CPU Package with Integrated MicroLEDs
Intel reveals a new design using glass substrates to embed MicroLED arrays directly into CPU packaging for aesthetics and status indicators.
hardwarebrief.com
September 29, 2026 at 7:47 PM
Intel Patents CPU Package with Integrated MicroLEDs
#Intel #MicroLED #Semiconductor #CPUDesign #TechInnovation
#Intel #MicroLED #Semiconductor #CPUDesign #TechInnovation
September 15, 2026 at 8:07 PM
Join our team in Penang as an Atom/Quark CPU Design Verification Engineer! Immerse yourself in innovation and advance your career. #EngineeringJobs #Penang #CPUdesign educativ.net/jobs/job/326...
February 26, 2025 at 11:28 AM
Join our team in Penang as an Atom/Quark CPU Design Verification Engineer! Immerse yourself in innovation and advance your career. #EngineeringJobs #Penang #CPUdesign educativ.net/jobs/job/326...
🚀 Dive into the future of tech! Apply now for the CPU Design Engineering Intern position at ECO3, Ecospace Campus 2A. Propel your career in tech innovation! #TechJobs #InternshipOpportunity #CPUDesign educativ.net/jobs/job/310...
February 2, 2025 at 11:31 AM
🚀 Dive into the future of tech! Apply now for the CPU Design Engineering Intern position at ECO3, Ecospace Campus 2A. Propel your career in tech innovation! #TechJobs #InternshipOpportunity #CPUDesign educativ.net/jobs/job/310...
This video shows my Graphics Processing Unit (GPU) Logisim component in my CPU design. My GPU can do blits, sprites, lines, polygons, & text. My GPU component is available for download on my Github page:
https://github.com/mrmcsoftware/GPU4Logisim
#GPU #Logisim #CPUdesign #CPU #simulator [...]
https://github.com/mrmcsoftware/GPU4Logisim
#GPU #Logisim #CPUdesign #CPU #simulator [...]
Very Fast and Versatile GPU Component for my Logisim CPU / Computer (Blits, Sprites, Lines, Polygons, Circles, and Text)
This video shows my Graphics Processing Unit (GPU) Logisim component in my CPU design. My GPU can do blits, sprites, lines, polygons, and text faster than any other currently existing simulated Logisim GPU. My GPU component is available for download on my Github page: https://github.com/mrmcsoftware/GPU4Logisim This CPU is based on the 16 instruction microprocessor I designed for a homework assignment many years ago, though it now has many more instructions.
www.youtube.com
December 5, 2025 at 5:37 PM
This video shows my Graphics Processing Unit (GPU) Logisim component in my CPU design. My GPU can do blits, sprites, lines, polygons, & text. My GPU component is available for download on my Github page:
https://github.com/mrmcsoftware/GPU4Logisim
#GPU #Logisim #CPUdesign #CPU #simulator [...]
https://github.com/mrmcsoftware/GPU4Logisim
#GPU #Logisim #CPUdesign #CPU #simulator [...]
Design of Complementary Metal–Oxide–Semiconductor Encoder/Decoder with Compact Circuit Structure for Booth Multiplier
www.mdpi.com/2673-4591/10...
By Yu-Nsin Wang and Yu-Nsin Wang
From the 8th Eurasian Conference on Educational Innovation 2025
#CPUDesign #ALU
www.mdpi.com/2673-4591/10...
By Yu-Nsin Wang and Yu-Nsin Wang
From the 8th Eurasian Conference on Educational Innovation 2025
#CPUDesign #ALU
December 23, 2025 at 2:41 PM
Design of Complementary Metal–Oxide–Semiconductor Encoder/Decoder with Compact Circuit Structure for Booth Multiplier
www.mdpi.com/2673-4591/10...
By Yu-Nsin Wang and Yu-Nsin Wang
From the 8th Eurasian Conference on Educational Innovation 2025
#CPUDesign #ALU
www.mdpi.com/2673-4591/10...
By Yu-Nsin Wang and Yu-Nsin Wang
From the 8th Eurasian Conference on Educational Innovation 2025
#CPUDesign #ALU
How CPUs are Designed and Built: Fundamentals of Computer Architecture #Technology #Hardware #Microprocessors #CPUDesign #ComputerArchitecture #TechEducation
How CPUs are Designed and Built: Fundamentals of Computer Architecture
We all think of the CPU as the
puretech.news
February 13, 2025 at 6:30 AM
How CPUs are Designed and Built: Fundamentals of Computer Architecture #Technology #Hardware #Microprocessors #CPUDesign #ComputerArchitecture #TechEducation
“No, the actual reason AMD won't make a dual-V-Cache chip is much simpler: it would be pointless and a waste of money.”
#cpudesign #semiconductors
#cpudesign #semiconductors
AMD Reveals Real Reason It Won't Put 3D V-Cache On Multiple CCDs
After persistent rumors refused to recede, AMD steps in with a clear explanation why dual-CCD V-Cache doesn't exist.
hothardware.com
January 8, 2025 at 6:58 PM
“No, the actual reason AMD won't make a dual-V-Cache chip is much simpler: it would be pointless and a waste of money.”
#cpudesign #semiconductors
#cpudesign #semiconductors
Cuzco's static scheduling assumes L1 cache hits, replaying instructions on misses. This approach raises questions about its effectiveness for general-purpose computing, particularly concerning memory latency and potential cascading failures. 🤔 #CPUdesign 2/6
September 1, 2025 at 1:00 AM
Cuzco's static scheduling assumes L1 cache hits, replaying instructions on misses. This approach raises questions about its effectiveness for general-purpose computing, particularly concerning memory latency and potential cascading failures. 🤔 #CPUdesign 2/6
Bulldozer architecture was critically examined. Its significant shortcomings were seen as a major factor impacting AMD's competitive position in the CPU market at the time. #CPUDESIGN 4/6
June 18, 2025 at 2:00 PM
Bulldozer architecture was critically examined. Its significant shortcomings were seen as a major factor impacting AMD's competitive position in the CPU market at the time. #CPUDESIGN 4/6
Overview: HN discussed an LFSR CPU running Forth. This unconventional design uses an LFSR for the program counter, introducing unique challenges for branching & addressing. It touches on historical designs & related concepts like OISC architectures. #CPUdesign 1/6
June 3, 2025 at 5:00 PM
Overview: HN discussed an LFSR CPU running Forth. This unconventional design uses an LFSR for the program counter, introducing unique challenges for branching & addressing. It touches on historical designs & related concepts like OISC architectures. #CPUdesign 1/6
[Blog] How to count with Binary Numbers: http://www.cpu-design.at/archive/2015/11/16/how-to-count-with-binary-numbers/ #CpuDesign
How to count with Binary Numbers
» How to count with Binary Numbers | a custom developed ...
www.cpu-design.at
December 2, 2024 at 1:36 PM
[Blog] How to count with Binary Numbers: http://www.cpu-design.at/archive/2015/11/16/how-to-count-with-binary-numbers/ #CpuDesign
[Blog] How to count with Binary Numbers: http://www.cpu-design.at/archive/2015/11/16/how-to-count-with-binary-numbers/ #Binary #CpuDesign
How to count with Binary Numbers
» How to count with Binary Numbers | a custom developed ...
www.cpu-design.at
December 2, 2024 at 1:36 PM
[Blog] How to count with Binary Numbers: http://www.cpu-design.at/archive/2015/11/16/how-to-count-with-binary-numbers/ #Binary #CpuDesign
Do you want to know how a CPU works on the transistor level?Follow my new blog adventure at http://www.cpu-design.at #vhdl #xilinx #cpudesign
CPU Design | a custom developed CPU – Gate by Gate…
| a custom developed CPU – Gate by Gate…
www.cpu-design.at
December 2, 2024 at 1:36 PM
Do you want to know how a CPU works on the transistor level?Follow my new blog adventure at http://www.cpu-design.at #vhdl #xilinx #cpudesign
Writing my next blog posting: "How to count with hex numbers" #CpuDesign
December 2, 2024 at 1:26 PM
Writing my next blog posting: "How to count with hex numbers" #CpuDesign
[Blog] How to count with Hexadecimal Numbers: http://www.cpu-design.at/archive/2015/11/22/how-to-count-with-hexadecimal-numbers/ #cpudesign #computerscience
How to count with Hexadecimal Numbers
» How to count with Hexadecimal Numbers | a custom devel...
www.cpu-design.at
December 2, 2024 at 1:21 PM
[Blog] How to count with Hexadecimal Numbers: http://www.cpu-design.at/archive/2015/11/22/how-to-count-with-hexadecimal-numbers/ #cpudesign #computerscience
[Blog] Binary Logic: http://www.cpu-design.at/archive/2016/01/26/binary-logic/ #CpuDesign
Binary Logic
» Binary Logic | a custom developed CPU – Gate by Gate…
www.cpu-design.at
December 2, 2024 at 11:06 AM
[Blog] Binary Logic: http://www.cpu-design.at/archive/2016/01/26/binary-logic/ #CpuDesign
[Blog] The ALU is connected to my CPU: http://www.cpu-design.at/archive/2016/03/26/the-alu-is-connected-to-the-cpu/ #cpudesign #geek #retro
The ALU is connected to the CPU!
» The ALU is connected to the CPU! | a custom developed ...
www.cpu-design.at
December 2, 2024 at 8:52 AM
[Blog] The ALU is connected to my CPU: http://www.cpu-design.at/archive/2016/03/26/the-alu-is-connected-to-the-cpu/ #cpudesign #geek #retro
[Blog] Storing ALU Results in a General Purpose Register: http://www.cpu-design.at/archive/2016/04/05/storing-alu-results-in-a-general-purpose-register/ #CpuDesign, #BinaryCode #Internals
Storing ALU Results in a General Purpose Register
» Storing ALU Results in a General Purpose Register | a ...
www.cpu-design.at
December 2, 2024 at 8:05 AM
[Blog] Storing ALU Results in a General Purpose Register: http://www.cpu-design.at/archive/2016/04/05/storing-alu-results-in-a-general-purpose-register/ #CpuDesign, #BinaryCode #Internals
[Blog] Loading 16-bit Memory Addresses: http://www.cpu-design.at/archive/2016/07/15/loading-16-bit-memory-addresses/ #cpudesign #electronics #ttl
Loading 16-bit Memory Addresses
» Loading 16-bit Memory Addresses | a custom developed C...
www.cpu-design.at
December 2, 2024 at 2:21 AM
[Blog] Loading 16-bit Memory Addresses: http://www.cpu-design.at/archive/2016/07/15/loading-16-bit-memory-addresses/ #cpudesign #electronics #ttl
[Blog] I’ve joined the homebuilt CPU Web-Ring! http://www.cpu-design.at/archive/2016/07/18/ive-joined-the-homebuilt-cpu-webring/ #cpudesign #electronics #ttl
I’ve joined the Homebuilt CPU WebRing!
» I’ve joined the Homebuilt CPU WebRing! | a custom deve...
www.cpu-design.at
December 2, 2024 at 2:16 AM
[Blog] I’ve joined the homebuilt CPU Web-Ring! http://www.cpu-design.at/archive/2016/07/18/ive-joined-the-homebuilt-cpu-webring/ #cpudesign #electronics #ttl
[CPU Blog]: Completing the MOV16 opcode: http://www.cpu-design.at/archive/2016/08/02/completing-the-mov16-opcode/ #cpudesign #assembly #electronics #ttl
Completing the MOV16 opcode
» Completing the MOV16 opcode | a custom developed CPU –...
www.cpu-design.at
December 2, 2024 at 1:50 AM
[CPU Blog]: Completing the MOV16 opcode: http://www.cpu-design.at/archive/2016/08/02/completing-the-mov16-opcode/ #cpudesign #assembly #electronics #ttl