IP-XACT, defined by IEEE 1685, is a standard that pulls together IP packaging, integration, and reuse. For anyone building modern SoCs (Systems on Chip), IP-XACT isn’t just another XML schema: it is a...

Kactus2 is a graphical EDA tool for designing SoCs, packaging reusable IP, creating hardware hierarchies, and integrating hardware and software. The post Kactus2 – graphical EDA tool based on the IP-XACT standard appeared first on LinuxLinks.

The Design & Verification Conference & Exhibition (DVCON 2026) is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electron...

Arteris (Nasdaq: AIP) has launched Magillem Packaging, a new software solution designed to accelerate semiconductor creation by simplifying IP block and chiplet integration. The product addresses growing challenges in chip design complexity, particularly in AI data centers and edge devices. Based on IEEE 1685 (IP-XACT) standard, Magillem Packaging enables engineering teams to efficiently package and prepare hundreds of components for integration into chiplets or SoCs. Key features include comprehensive IP reuse capabilities, correct-by-construction IEEE 1685-2022 generation, and scalable automated IP packaging generation. The solution has received endorsements from industry leaders including Andes Technology and MIPS, highlighting its potential to streamline SoC development and accelerate time-to-market for semiconductor companies.