The Design & Verification Conference & Exhibition (DVCON 2025) is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electron...

Members of the Accellera CDC (Clock Domain Crossing) Working Group share the history, accomplishments, and current status of the working group. For an extended version, see: https://www.youtube.com/watch?v=k52ED1FxyrU

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IP-XACT, defined by IEEE 1685, is a standard that pulls together IP packaging, integration, and reuse. For anyone building modern SoCs (Systems on Chip), IP-XACT isn’t just another XML schema: it is a...

VR Download is UploadVR's weekly hardware, technology, and industry trends show streamed live from virtual reality. You can read the latest at UploadVR.com. 0:00 - Intro 7:43 - Gorilla Tag & VRChat Set Usage Records https://www.uploadvr.com/vrchat-nye-user-record/ 15:52 - Apple's Open-Source On-D

The Design & Verification Conference & Exhibition (DVCON 2026) is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electron...

Workshop presented at DVCon U.S. 2025 As the IEEE 1800.2 UVM standard continues to evolve, Accellera's release of the latest reference implementation (2020.3.1) introduces significant enhancements for verification engineers. This workshop focuses on the practical aspects of adopting the new version, providing an overview of its performance and functional improvements, as well as guidance for a smooth transition. We examine the migration process from UVM 1.2, emphasizing how the challenges faced in earlier transitions have been addressed. Particular attention is given to backward compatibility and resources now available, such as the public GitHub repository, which supports faster delivery of bug fixes and migration aids. Viewers will also gain an understanding of the performance benefits introduced and how these enhancements can accelerate verification workflows compared to legacy versions. The workshop also provides an overview of functional improvements, including enhancements that reduce the need to maintain modified versions of the UVM library. Finally, we discuss potential future enhancements, including plans for reworking the Register Abstraction Layer (RAL). Presented by: Justin Refice, NVIDIA https://dvcon.org https://dvcon-proceedings.org https://accellera.org https://ieee.org

In AI it is easy to be distracted by hype and miss the real advances in technology and adoption that are making a difference today. Accellera hosted a panel at DAC on just this topic, moderated by Dan...

In this exclusive interview, Sanjay Gangal of Sanjay Tech Cafe speaks with Lu Dai, Chair of Accellera, about the organization’s pivotal role in shaping the front-end EDA standards landscape. Lu provides a deep dive into Accellera’s mission, widely adopted standards like SystemC, UVM, and UPF, and the organization’s expanding focus on AI’s impact in design and verification. Lu also highlights Accellera’s presence at DAC 2025, including the highly anticipated AI-focused luncheon panel featuring leaders from Cadence, AMD, Siemens, Synopsys, Microsoft, and NVIDIA. He previews the special engineering session on CDC and RDC standards, discusses the open and collaborative development approach, and invites viewers to engage, contribute feedback, and access resources such as IEEE 1801 and training videos via accellera.org. If you're involved in EDA, chip design, or system verification, this is a must-watch conversation on how standards are evolving to keep pace with AI and industry innovation. 👉 Don’t forget to like, comment, and subscribe for more in-depth industry interviews!