The Design & Verification Conference & Exhibition (DVCON 2025) is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electron...

The Design & Verification Conference & Exhibition (DVCON 2025) is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electron...

Introduction: At the recent DVCon US conference, a clear consensus emerged: agentic AI is poised to revolutionize semiconductor design, automatically generating RTL code and complex design blocks. However, industry leaders noted a critical bottleneck—while AI accelerates design, the verification and simulation cycles remain glacial, creating a net-zero productivity gain. For cybersecurity and IT professionals, this hardware development paradox offers a powerful analogy: accelerating offensive or defensive tools is useless if the underlying infrastructure and feedback loops cannot keep pace.

The Design & Verification Conference & Exhibition (DVCON 2026) is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electron...

Workshop presented at DVCon U.S. 2025 As the IEEE 1800.2 UVM standard continues to evolve, Accellera's release of the latest reference implementation (2020.3.1) introduces significant enhancements for verification engineers. This workshop focuses on the practical aspects of adopting the new version, providing an overview of its performance and functional improvements, as well as guidance for a smooth transition. We examine the migration process from UVM 1.2, emphasizing how the challenges faced in earlier transitions have been addressed. Particular attention is given to backward compatibility and resources now available, such as the public GitHub repository, which supports faster delivery of bug fixes and migration aids. Viewers will also gain an understanding of the performance benefits introduced and how these enhancements can accelerate verification workflows compared to legacy versions. The workshop also provides an overview of functional improvements, including enhancements that reduce the need to maintain modified versions of the UVM library. Finally, we discuss potential future enhancements, including plans for reworking the Register Abstraction Layer (RAL). Presented by: Justin Refice, NVIDIA https://dvcon.org https://dvcon-proceedings.org https://accellera.org https://ieee.org

Workshop presented at DVCon U.S. 2025 Full title: Introduction of IEEE 1801-2024 (UPF 4.0) -- Improvements for the Specification and Verification of Low-Power Intent As advanced low-power architectures have become more pervasive in the industry, the complexity of these architectures has driven new methodologies for the verification, implementation, and reuse of power intent specifications. Modern low-power designs place requirements that span from enabling more flexible IP design reuse to providing well defined interfaces between analog and digital components in simulation. The IEEE 1801-2024 (UPF 4.0) standard provides several key enhancements that are required to keep pace with these innovations in low-power design. The workshop provides an overview of the enhancements to the standard from both a conceptual and a command level. New concepts such as virtual supply nets, refinable macros, and UPF libraries are introduced, as well as rearchitected features with respect to interfacing between analog and digital simulation and advanced state retention modeling. While the new IEEE 1801-2024 standard provides numerous detailed clarifications and enhancements to the previous version, this workshop focuses on the key changes that will impact most designers and changes that enable new functionality. In the six years since IEEE 1801-2018 was introduced, there have been a number of trends in design that required additional features in the standard to support. Key among these is an increasing need for co-verification of analog and mixed-signal content. Another trend is that IP providers are providing pre-verified low-power IP to their customers, but struggle to provide a flexible IP for implementation in multiple design contexts while preserving the verification sign-off on the blocks. To address these trends, IEEE 1801-2024 provides new features such as Value Conversion Methods (VCM) and HDL tunneling that help bridge the gap between the analog and digital designs, and the concept of a refinable macro to address the IP reuse requirements. Real-world usage of the previous standard (IEEE 1801-2018) has prompted clarifications and enhancements that will have a significant impact on users of the standard. For example, the modeling of state retention has been entirely reworked to provide better modeling of the retention power intent and to more accurately define requirements on the retention control signals in each phase of state retention. The new standard also codifies some common design practices to make a clear, more consistent implementation across vendors. The new concept of virtual supplies is one such case. It removes the ambiguity that exists today when supplies are used to provide port constraints or to simplify power state definitions, but do not imply a physical supply net in implementation. This workshop introduces these new concepts and their associated commands and provides an overview of the major semantic and syntax changes introduced by IEEE 1801-2024. This understanding will help users transition to the new standard and improve the quality of advanced low-power architectures and design environments. Authors: -- John Decker, IEEE P1801 Workgroup Chair -- Daniel Cross, Cadence -- Amit Srivastava, IEEE P1801 Workgroup Vice-Chair -- Lakshmanan Balasubramanian, IEEE P1801 Workgroup Secretary -- Marcelo Glusman, Cadence -- Medaramitta Jeevan, Siemens -- Gabriel Chidolue, Siemens -- Rick Koster, Siemens -- Raguvaran Easwaran, Intel -- Paul Bailey, Nordic Semiconductor -- Progyna Khondkar, Cadence https://dvcon.org https://dvcon-proceedings.org https://accellera.org https://ieee.org

ALT: a globe is surrounded by the letters r and h

Welcome to Accellera Systems Initiative's official YouTube channel. Accellera is an independent and collaborative organization with the mission to create and advance system-level design, modeling, a...

Munich, Germany – 9th September 2025- The Design and Verification Conference & Exhibition Europe (DVCon Europe), sponsored by Accellera Systems Initiative, has announced an extensive technical …

YouTube video by V3LCR0 OFFICIAL

Hardware engineers take great care to ensure that their designs are correct. Unlike bugs in software, which can often be easily fixed with a quick patch, mistakes in hardware can be exceedingly diffic...

In this week’s Fish Fry podcast, I discuss design and verification with Tom Fitzpatrick – General Chair of DVCon 2025. Tom and I explore this year’s expo and conference, the motivation behind…

In this week’s podcast, I chat about the future of EDA, the details of DVCon2024, and the feasibility of artificial intelligence for design verification with Tom Fitzpatrick - DVCon 2024 Conference Ge...