“juni, you’re the only puppy i know who understands systemverilog”
April 23, 2025 at 1:47 AM
“juni, you’re the only puppy i know who understands systemverilog”
shout-out to @marathonteam.bungie.net runner "SystemVerilog", A+ well done
June 18, 2026 at 4:53 AM
shout-out to @marathonteam.bungie.net runner "SystemVerilog", A+ well done
chaotic neutral: systemverilog constrained random is a tabletop rpg
August 12, 2025 at 12:14 AM
chaotic neutral: systemverilog constrained random is a tabletop rpg
Huh SystemVerilog *is* better
September 23, 2026 at 9:11 AM
Huh SystemVerilog *is* better
Vibe coding with Erik Meijer using LLMs to generate circuits specified and formally verified in Agda and Lean, LLM transliterated into SystemVerilog with corresponding UVM tests and SVA formal properties for model checking, as well as LLM generated FSM Mermaid diagrams.
May 30, 2025 at 9:00 PM
Vibe coding with Erik Meijer using LLMs to generate circuits specified and formally verified in Agda and Lean, LLM transliterated into SystemVerilog with corresponding UVM tests and SVA formal properties for model checking, as well as LLM generated FSM Mermaid diagrams.
3,488 triangle edition of the Utah teapot, environment mapped by a hardware geometry engine through my recreation of the SST-1 fixed function pipeline. Important note: because it is the Utah teapot, the bottom is missing. Wouldn't be right to add it.
100% FPGA hardware. Entirely SystemVerilog.
100% FPGA hardware. Entirely SystemVerilog.
February 18, 2026 at 3:44 AM
3,488 triangle edition of the Utah teapot, environment mapped by a hardware geometry engine through my recreation of the SST-1 fixed function pipeline. Important note: because it is the Utah teapot, the bottom is missing. Wouldn't be right to add it.
100% FPGA hardware. Entirely SystemVerilog.
100% FPGA hardware. Entirely SystemVerilog.
if this 100% FPGA demo is passing for a shader, that’s probably my cue to release it. this is an early demo of my own work to replicate the 3dfx sst-1 pipeline in systemverilog. there is a non-canon geometry engine driving it from within the FPGA for kicks.
April 16, 2026 at 1:52 AM
if this 100% FPGA demo is passing for a shader, that’s probably my cue to release it. this is an early demo of my own work to replicate the 3dfx sst-1 pipeline in systemverilog. there is a non-canon geometry engine driving it from within the FPGA for kicks.
It's an FPGA-based board that lets you program the application, driver, and hardware layers in Lua, C, and VHDL/SystemVerilog, and it starts at $29.
https://itsfoss.com/news/elm11-feather-announcement/
https://itsfoss.com/news/elm11-feather-announcement/
July 11, 2026 at 3:12 AM
It's an FPGA-based board that lets you program the application, driver, and hardware layers in Lua, C, and VHDL/SystemVerilog, and it starts at $29.
https://itsfoss.com/news/elm11-feather-announcement/
https://itsfoss.com/news/elm11-feather-announcement/
🌟 Silent star of the day
uhdm2rtlil — Yosys SystemVerilog Parser - UHDM 2 RTLIL Yosys Pass
#indiedev #opensource
uhdm2rtlil — Yosys SystemVerilog Parser - UHDM 2 RTLIL Yosys Pass
#indiedev #opensource
uhdm2rtlil · SilentStars
Yosys SystemVerilog Parser - UHDM 2 RTLIL Yosys Pass
capuz.github.io
July 12, 2026 at 6:25 AM
🌟 Silent star of the day
uhdm2rtlil — Yosys SystemVerilog Parser - UHDM 2 RTLIL Yosys Pass
#indiedev #opensource
uhdm2rtlil — Yosys SystemVerilog Parser - UHDM 2 RTLIL Yosys Pass
#indiedev #opensource
The SystemVerilog standard is wild. 1300 pages that manage to say absolutely nothing about how the language works, apart from gems like this
February 5, 2025 at 1:31 PM
The SystemVerilog standard is wild. 1300 pages that manage to say absolutely nothing about how the language works, apart from gems like this
SystemVerilog frontend for Yosys
github.com/povik/yosys-...
github.com/povik/yosys-...
GitHub - povik/yosys-slang: SystemVerilog frontend for Yosys
SystemVerilog frontend for Yosys. Contribute to povik/yosys-slang development by creating an account on GitHub.
github.com
November 23, 2024 at 10:36 AM
SystemVerilog frontend for Yosys
github.com/povik/yosys-...
github.com/povik/yosys-...
im also a dog who understands systemverilog (kinda!)
April 23, 2025 at 3:10 AM
im also a dog who understands systemverilog (kinda!)
🐧 **Verible – SystemVerilog parser, linter, formatter and language server**
Verible is a suite of SystemVerilog developer tools providing style linting, formatting, parsing, project analysis and language server support. The post Verible – SystemVerilog parser, linter, form...
📰 Source […]
Verible is a suite of SystemVerilog developer tools providing style linting, formatting, parsing, project analysis and language server support. The post Verible – SystemVerilog parser, linter, form...
📰 Source […]
Original post on igeek.gamer-geek-news.com
igeek.gamer-geek-news.com
September 15, 2026 at 12:06 AM
🐧 **Verible – SystemVerilog parser, linter, formatter and language server**
Verible is a suite of SystemVerilog developer tools providing style linting, formatting, parsing, project analysis and language server support. The post Verible – SystemVerilog parser, linter, form...
📰 Source […]
Verible is a suite of SystemVerilog developer tools providing style linting, formatting, parsing, project analysis and language server support. The post Verible – SystemVerilog parser, linter, form...
📰 Source […]
Hardware level CNN in SystemVerilog
Author designed or implemented the architecture of a CNN directly in hardware, rather than software, using SystemVerilog. This task implies that the CNN is being described in a way that it could potentially be synthesized into actual hardware, like an ASIC.
Author designed or implemented the architecture of a CNN directly in hardware, rather than software, using SystemVerilog. This task implies that the CNN is being described in a way that it could potentially be synthesized into actual hardware, like an ASIC.
November 4, 2024 at 7:44 AM
Hardware level CNN in SystemVerilog
Author designed or implemented the architecture of a CNN directly in hardware, rather than software, using SystemVerilog. This task implies that the CNN is being described in a way that it could potentially be synthesized into actual hardware, like an ASIC.
Author designed or implemented the architecture of a CNN directly in hardware, rather than software, using SystemVerilog. This task implies that the CNN is being described in a way that it could potentially be synthesized into actual hardware, like an ASIC.
writing entirely too much tcl and systemverilog for a sunday evening
August 14, 2023 at 3:31 AM
writing entirely too much tcl and systemverilog for a sunday evening
🐧 **5 Best Free and Open Source Verilog Linter Tools**
Discover the best Verilog and SystemVerilog linting tools for static analysis, code quality, and HDL development. The post 5 Best Free and Open Source Verilog Linter Tools appeared first on LinuxLi...
📰 Source: LinuxLinks
🔗 Link […]
Discover the best Verilog and SystemVerilog linting tools for static analysis, code quality, and HDL development. The post 5 Best Free and Open Source Verilog Linter Tools appeared first on LinuxLi...
📰 Source: LinuxLinks
🔗 Link […]
Original post on igeek.gamer-geek-news.com
igeek.gamer-geek-news.com
September 26, 2026 at 7:53 AM
🐧 **5 Best Free and Open Source Verilog Linter Tools**
Discover the best Verilog and SystemVerilog linting tools for static analysis, code quality, and HDL development. The post 5 Best Free and Open Source Verilog Linter Tools appeared first on LinuxLi...
📰 Source: LinuxLinks
🔗 Link […]
Discover the best Verilog and SystemVerilog linting tools for static analysis, code quality, and HDL development. The post 5 Best Free and Open Source Verilog Linter Tools appeared first on LinuxLi...
📰 Source: LinuxLinks
🔗 Link […]
systemverilog forever and ever
August 23, 2026 at 5:06 AM
systemverilog forever and ever
Chip was written in Spade HDL (spade-lang.org), which transpiles down to SystemVerilog. That's then fed into a LibreLane build process that turns the verilog into transistors. All open source!
Spade | Spade Hardware Description Language
spade-lang.org
December 4, 2025 at 2:51 PM
Chip was written in Spade HDL (spade-lang.org), which transpiles down to SystemVerilog. That's then fed into a LibreLane build process that turns the verilog into transistors. All open source!
Live de @rancune.org sur les FPGA qui est en cours, foncez si le sujet vous intéresse.
www.twitch.tv/rancune_
www.twitch.tv/rancune_
Rancune_ - Twitch
[08.06.2025] Systemverilog
www.twitch.tv
June 8, 2025 at 7:28 PM
Live de @rancune.org sur les FPGA qui est en cours, foncez si le sujet vous intéresse.
www.twitch.tv/rancune_
www.twitch.tv/rancune_
Not even SystemVerilog tbh
You get gates and nets. Need generate loops? Write a verilog generator in Lisp
You get gates and nets. Need generate loops? Write a verilog generator in Lisp
May 23, 2025 at 4:16 AM
Not even SystemVerilog tbh
You get gates and nets. Need generate loops? Write a verilog generator in Lisp
You get gates and nets. Need generate loops? Write a verilog generator in Lisp
This is what the core of the Haskell Lava DSL implementation looks like. It is a bunch of point-free style recursive combinators that capture the recursive structure and layout of the butterfly network. After evaluation, this produces a SystemVerilog file with layout annotations for
September 22, 2025 at 7:10 AM
This is what the core of the Haskell Lava DSL implementation looks like. It is a bunch of point-free style recursive combinators that capture the recursive structure and layout of the butterfly network. After evaluation, this produces a SystemVerilog file with layout annotations for
