#ThreadGroup
Have you requested your invite? Last year's social had 100+ attendees from all across the smart home & building spaces. Join the network that's shaping the future of #IoT at this can't miss event!

Request your invite — spots limited: docs.google.com/forms/d/e/1F...

#ThreadGroup #NetworkingSocial
Thread Group Networking Social at CES 2027: Request for Invitation
Join us for an exclusive evening of networking, bites, and cocktails on January 7, 2027, during CES week! Connect with Thread members, industry leaders, and smart home innovators in an engaging settin...
docs.google.com
November 9, 2026 at 10:09 PM
Want to be among the first to hear some exciting news from Thread Group? Interested in Thread membership? We are bringing the smart home community together during CES 2027!

Spots are limited! Request your invitation: docs.google.com/forms/d/e/1F...

#ThreadGroup #CES2027 #NetworkingEvent
October 26, 2026 at 8:17 PM
It was great to see the #ThreadGroup Board of Directors gathered together for our face-to-face meeting in New Orleans, Louisiana!

Missed this #MembersMeeting? Make sure to sign up for the next one in May 2027.

threadgroup.org/thread-group...

#ThreadGroup #Meeting #IoT #Board
October 22, 2026 at 5:25 PM
More Efficiency. More with Thread.

#ThreadGroup member, #Aeotec, showcased their Matter over Thread devices at IFA 2026.

"The self-healing mesh is a very important feature we want to offer our clients when building a smart home. That's the way we see #Matter and Thread working together."
October 21, 2026 at 8:09 PM
More Battery Life. More with Thread.

Thread Group member, Aqara, was showcasing their Built on Thread devices, like sensors and locks, at #IFA2026. They choose Thread for its long battery life and reliability.

#MoreWithThread #ThreadGroup #ReliableIoT #SmartHome
October 6, 2026 at 5:36 PM
Did you miss the #ThreadGroup & #BroadbandForum webinar? Watch below to hear about their liaison agreement and explore #interoperability opportunities, service provider implications, and the roadmap toward more unified smart home and building ecosystems.

www.youtube.com/watch?v=kDET...
Connecting IoT Mesh Networks w/ Broadband Infrastructure: A New Path for Service Providers - Webinar
YouTube video by Broadband Forum
www.youtube.com
September 28, 2026 at 8:20 PM
#ThreadGroup is working to bring the benefits of Thread #technology to a #SubGHz PHY, creating a path toward a common, IP-based open standard for applications like building automation, healthcare, industrial sensing, & more.

Read our blog to learn more:

threadgroup.org/newsroom/blo...
September 21, 2026 at 3:35 PM
#ThreadGroup recently published the #Thread 1.4 for #SmartBuildings white paper, which dives into how Thread’s low-power mesh networking can help building owners, system integrators & manufacturers create interoperable networks.

Read the #whitepaper: www.threadgroup.org/Portals/0/Do...
September 15, 2026 at 5:24 PM
#ThreadGroup recently published a white paper with #KNX Association, which explores how #KNXIoT & Thread come together to extend KNX into the IPv6 world, enabling reliable wireless connectivity, low-power devices, and more flexible retrofit opportunities.

www.threadgroup.org/Portals/0/Do...
September 14, 2026 at 6:49 PM
#ThreadGroup will be at #TheThingsConference2026!

Esko Dijk will break down how Thread works, its features, and why it's beneficial for #IoT device makers. Henk Veldhuis will be on a panel talking about the future of IoT and Thread.

Register here: www.thethingsconference.com/tickets
September 10, 2026 at 5:18 PM
That's a wrap on #IFA2026! At our #networking social, we discussed the value of Thread through insightful conversations and panel discussions. Stay tuned for what's next!

Want to know more about Thread membership? Visit www.threadgroup.org/thread-group...

#ThreadGroup #BuiltOnThread #IoT
September 9, 2026 at 3:52 PM
The countdown to #IFA2026 is on! #ThreadGroup is hosting an exclusive event on Sept 6th. Join us for #networking and learn more about the future of #IoT by connecting with industry leaders and Thread representatives.

Spots are limited, request your invite docs.google.com/forms/d/e/1F...
August 26, 2026 at 4:15 PM
Congratulations to our Innovation Enabler Award winners, Sensereo & mash!

The #ThreadGroup #Innovation Enabler Program provides start-up companies the opportunity to define #IoT through access to #Thread’s technology and their members.

Learn more: www.threadgroup.org/Innovation-E...
August 20, 2026 at 4:56 PM
The correct names for an instance are a thread or invocation, the correct names for a block is a workgroup or threadgroup, the correct names for a whole set of blocks is a dispatch or a grid. The in-between bit, where the workgroups get grouped, might be a wave, wavefront, warp, batch, pool...
May 31, 2025 at 11:24 AM
We're proud to see Tom Sciorilli representing #Inventures client, #ThreadGroup, at #Unify2026!

As a certification expert, Tom help clients develop and manage certification programs that drive interoperability, quality, and industry adoption.

#IoT

www.linkedin.com/posts/unify2...
#unify2026 #unify #csa #threadgroup #threadcertification #iot #builtonthread | Thread Group
Coming to #Unify2026? Don't miss our VP of Certification, Tom Sciorilli, talk all things certification and the path to interoperability and market readiness! It's not too late to register: https://cs...
www.linkedin.com
June 8, 2026 at 4:44 PM
TurboQuant model weight compression support added to Llamacpp
Discussion | hackernews | Author: lastdong
TurboQuant model weight compression support added to Llamacpp
Summary TQ3_1S (3-bit, 4.0 BPW) and TQ4_1S (4-bit, 5.0 BPW) weight quantization using WHT rotation + Lloyd-Max centroids V2.1 fused Metal kernel: zero threadgroup memory, cooperative SIMD rotation...
github.com
April 4, 2026 at 10:13 AM
Dropped a wave-size agnostic threadgroup local bitonic sort implementation in HLSL (mainly to help with data divergence locally or/and complement global radix sort variants with up to 12 bits per pass): github.com/pm4rtx/threa...
GitHub - pm4rtx/threadgroup_bitonic_sort_hlsl: An HLSL implementation of a thread group wide bitonic sort for GPU
An HLSL implementation of a thread group wide bitonic sort for GPU - pm4rtx/threadgroup_bitonic_sort_hlsl
github.com
June 25, 2025 at 5:22 AM
Naming GPU things in the Rust Compiler and Standard Library
Thanks for the comments, that’s all very valuable input! Extending on the name for the group of threads that runs on a SIMD unit, warp/wave/wavefront/subgroup * Warp is coined by nvidia (comes from weaving as jdahlstrom mentioned above) * Wavefront is coined by amd * Subgroup is from Khronos (the vendor-crossing APIs like OpenCL) * Wave is from DirectX * Simdgroup is from Apple/Metal * Maybe threadgroup? (but that means workgroup on Apple/Metal) * Maybe executiongroup? I feel like none of these choices is particularly appealing. Subgroup does not feel fitting (analogous on CPUs, something running on a core is not a subprocess, but called a _thread_). Warp doesn’t resonate with me so far (in its original meaning in weaving, it describes a single, orthogonal thread, but we want to describe a certain _group_ of threads). Simdgroup doesn’t make sense to me as it’s not a group of SIMDs (that sounds like a better name for an SM on nvidia or WGP on amd). With the lack of self-explanatory names, I’m currently leaning towards _wave_ as it’s short and unambiguous. A slightly refined structured API, without nesting and extended with launch_sized_workgroup_mem: /// Everything from launch scope struct Launch {} impl Launch { /// Workgroup id (x/y/z) fn workgroup_x() -> u32; /// Number of launched workgroups (x/y/z) fn workgroups_x_len() -> u32; } /// Everything from workgroup scope struct Workgroup {} impl Workgroup { /// Number of waves in a workgroup fn waves_len() -> u32; /// Number of threads in the workgroup (x/y/z) fn threads_x_len() -> u32; /// Thread id inside workgroup (x/y/z) fn thread_x() -> u32; /// Maybe makes sense to expose gpu_launch_sized_workgroup_mem() here /// as it is on the workgroup scope? fn launch_sized_mem<T>() -> *mut T; } /// Everything from wave scope struct Wave {} impl Wave { /// Number of threads in the wave /// ~= Number of lanes in a SIMD unit fn len() -> u32; /// Thread/lane id inside wave fn thread_id() -> u32; // Could include wave intrinsics like ballot, read_first_lane, reduces, etc. here } As a place for writing this down, I think the module documentation of `core::gpu` would fit well. New/changed naming: * workgroup-shared memory → **workgroup memory** * The thing that launches a gpu-kernel: **runtime** (i.e. an application calls into the runtime, which then launches the gpu-kernel on the GPU) ### Regarding address spaces I agree that something like `AddrspacePtr<T, const /* enum? */ Addrspace ADDRSPACE>` akin to `VolatilePtr` would be nice. I tried to take a look at implementing it but didn’t get very far. I didn’t find an easy way to define a type where the implementation is in the compiler. We want an `AddrspacePtr` to be Sized but the size depends on the generic ADDRSPACE argument (in that sense it’s different from `extern type` which doesn’t have a size and cannot be stored by value). Adding it as `ty::AddrspacePtr` turned out to be a rather large change (maybe adding an addrspace argument to `ty::RawPtr` would make it easier?). But that can be a separate discussion. ### Misc > In my opinion for vendor specific things we should stick to the vendor specific naming. […] I agree. > However, for the code in `core::intrinsics` this approach was never taken, so I do not know if this approach is possible and desirable for _rustc_intrinsics_. So this might rather be the way for intrinsic wrappers. Right, the `core::gpu` module should be a wrapper for (vendor specific) intrinsics. I think it’s something we can eventually stabilize (compared to (rustc)intrinsics, which are mostly not stabilized). > `gpu::available_*_parallelism` I agree to the other answer above, the _available parallelism_ doesn’t match what we want here (the name does make sense in std::thread for ~cpu-count). The GPU launch/workgroup sizes are specified on the CPU when launching a gpu-kernel and the kernel wants to get these exact, specified sizes.
internals.rust-lang.org
December 25, 2025 at 12:50 AM
As minimum as possible! (I'd like to not noticeably heat up or drain people's handheld devices. Probably won't hit that target, but I'd like to try.)

Would you have 1 instance per hex or per chunk? (I've read small instances are a bad idea due to something something threadgroup sizes?)
March 5, 2025 at 9:13 AM
macOS VMs under-report Metal capability, so llama.cpp picked slow kernels. A process-scoped shim raises the reported Apple family and threadgroup memory to 64KB: on an M1 Ultra, TinyLlama prompts ran 11.08x faster and generation 16.36x.
The tax was reporting, not silicon.
August 13, 2026 at 12:45 AM
thanks! your method makes it easy :) well, that and the glory of atomic splatting. who needs sorting etc :) on this m1 macbook its plenty fast without the prefixsum loadbalancer too, i think because the M1 is good at unbalanced threadgroup workloads? idk. :) this is 'dumbest possible impl'.
June 25, 2026 at 7:56 PM
i didnt implement their fancy load balancer or occlusion culling, tho they are recommended for Serious Implementers for sure; this is just one-splat per threadgroup and then for loop, single compute shader ftw. for the coc, I probably want some different warp of the gaussian to represent the disc
June 25, 2026 at 6:23 PM
If the # of regions is kept relatively small, I'd probably preprocess the regions into threadgroup counts and buffer offsets, and have each thread check region containment akin to detecting if a pixel is within viewport in compute. Can early out to avoid duplicate work in overlapping regions too.
May 21, 2025 at 7:25 PM
Mohamed Amine Bergach: Beating vDSP: A 138 GFLOPS Radix-8 Stockham FFT on Apple Silicon via Two-Tier Register-Threadgroup Memory Decomposition https://arxiv.org/abs/2603.27569 https://arxiv.org/pdf/2603.27569 https://arxiv.org/html/2603.27569
March 31, 2026 at 6:30 AM