#cpld
did you see my 2 layer BGA CPLD board?
September 29, 2026 at 2:36 AM
Probably does. Kind of*. Core is a spider 48 which is a cpld implementation of a normal 48, but as is my way, I've added a Yamaha OPL , philips SA1099, SP0256 allophone chip (of currah uspeech fame), a midi interface and Bluetooth.

*If it works at all
September 21, 2026 at 5:55 PM
CPLD/FPGA Firmware Engineer, Annapurna Labs, ML Accelerator Systems Firmware - Austin Job educativ.net/jobs/job/65171...
September 12, 2026 at 7:43 PM
自分OLDPC向けハードでロジック回路簡略化でCPLD使いになったかも;D
tangさんVHDLでかけますん?
September 11, 2026 at 3:08 PM
CPLD最新触ってなくてfpgaに来ましたがもう
tang nano20kじゃたりん!
September 11, 2026 at 3:07 PM
Here it is with an LCD display, battery backed up RAM, a real-time clock, and all the glue logic pushed onto a CPLD (that I also made myself).
September 10, 2026 at 9:04 AM
I wonder if there's some kind of memory converter chip that can bridge the SPI used by these kinds of serial PSRAMs to parallel address and data buses. I could probably make one out of a CPLD but...
September 9, 2026 at 11:39 AM
I don't have any experience with GAL PLAs, I have always used the CPLD-based replacements.

If it looks like a bad PLA but the PLA chip itself tests okay, look at U15 and U27.
September 8, 2026 at 2:02 PM
this xbox 360 horrorshow I crafted today

tonasket 16mb
mounted rp2040:
- SPI
- CPLD JTAG
- POST reading

custom 2040 firmware based on Mate Kukri's PicoFlasher v4, hmu for a source, probably won't git release as it's an edge case
September 2, 2026 at 3:34 AM
CPLD VGA! unlike the ch32v003 version, this works I used a monostable to make lines like an ADC :]
Thats my CPLD board :]
August 25, 2026 at 4:52 AM
Attempting to play with an altera CPLD, here I have finished the power and jtag connections, now I cant find out if it survived the process!
August 22, 2026 at 9:12 PM
今日のZennトレンド

Proxmox VEでAMD SEV-SNPを試してみる
Proxmox VEでAMD SEV-SNPを有効化し、仮想マシンを起動させる手順と検証内容をまとめた記事です。
BIOSでSEV-SNP等の設定を有効にした後、Proxmoxの仮想マシン設定でSEV-SNPを指定してUbuntu Serverを構築しています。
最終的に仮想マシン内での動作確認を行い、snpguestを使用してAttestation Reportを取得できることを確認しています。
Proxmox VEでAMD SEV-SNPを試してみる
Proxmox VEでAMD SEV-SNPを有効化し、実際に仮想マシンを起動してみます。 1. 環境以下の環境で検証しました。マザーボード: Supermicro H12SSW-NT (BIOS Version 3.6, CPLD Version A2.C2.01)CPU: AMD EPYC 7543PPSP FirmwareBootLoader Version: 0.13.0.80SMU FW
zenn.dev
August 11, 2026 at 9:53 AM
Inside the Beckhoff BK5200 – the design of an industrial DeviceNet-to-CAN coupler: A teardown of Beckhoff’s BK5200 DeviceNet-to-K-Bus coupler reveals how it links modular industrial I/O terminals to a CAN-based DeviceNet network.
The BK5200 separates its switching power supply, C166/CAN logic, and…
Inside the Beckhoff BK5200 – the design of an industrial DeviceNet-to-CAN coupler
A teardown of Beckhoff’s BK5200 DeviceNet-to-K-Bus coupler reveals how it links modular industrial I/O terminals to a CAN-based DeviceNet network. The BK5200 separates its switching power supply, C166/CAN logic, and isolated DeviceNet/K-Bus interface across three PCBs. Its Siemens SAB-C165-LM microcontroller works with a Philips SJA1000T CAN controller, Altera EPM7032 CPLD, 64 KB SRAM, and 32 KB EEPROM. The coupler supports up to 64 K-Bus terminals, uses a 24 V supply, and offers 125/250/500 kBaud DeviceNet rates. A resistor soldered directly onto an Altera CPLD pin suggests an unexplained repair or possible factory modification. Full article on the elektroda homepage.
www.elektroda.com
August 9, 2026 at 12:13 PM
Beckhoff BK5200 od środka - budowa przemysłowego łącznika DeviceNet z CAN: Beckhoff BK5200 to rozebrany przemysłowy łącznik DeviceNet, ujawniający wielopłytkową architekturę łączącą terminale I/O K-Bus z magistralą CAN.
Główną logikę tworzą 16-bitowy mikrokontroler Siemens SAB-C165-LM, kontroler…
Beckhoff BK5200 od środka - budowa przemysłowego łącznika DeviceNet z CAN
Beckhoff BK5200 to rozebrany przemysłowy łącznik DeviceNet, ujawniający wielopłytkową architekturę łączącą terminale I/O K-Bus z magistralą CAN. Główną logikę tworzą 16-bitowy mikrokontroler Siemens SAB-C165-LM, kontroler CAN Philips SJA1000T oraz CPLD Altera EPM7032LC44-15. BK5200 obsługuje do 64 terminali K-Bus, pracuje z zasilaniem 24 V i oferuje prędkości DeviceNet 125/250/500 kBaud. Pamięć obejmuje dwa SRAM PDM41256SA15SO po 32 KB oraz EEPROM Atmel AT28C256 32 KB, a komunikację izolują transoptory HCPL-0601. Na płycie CPLD widnieje nietypowy rezystor przewlekany dolutowany do nóżki układu Altera; nie ustalono, czy to naprawa serwisowa czy fabryczna poprawka. Cały artykuł na stronie głównej elektroda.
www.elektroda.pl
August 9, 2026 at 11:54 AM
SDE - CPLD / FPGA - Seattle Job educativ.net/jobs/job/62977...
July 31, 2026 at 7:25 PM