Spent all night debugging my RISC-V emulator. I got a simple Rust program to build for the riscv target, and so I wanted to try to load it in the emulator.
I made the emulator take one CLI argument as a file path to load the binary from, copied my built riscv binary over, but...
I made the emulator take one CLI argument as a file path to load the binary from, copied my built riscv binary over, but...
September 26, 2026 at 6:58 AM
Spent all night debugging my RISC-V emulator. I got a simple Rust program to build for the riscv target, and so I wanted to try to load it in the emulator.
I made the emulator take one CLI argument as a file path to load the binary from, copied my built riscv binary over, but...
I made the emulator take one CLI argument as a file path to load the binary from, copied my built riscv binary over, but...
damn TIL the titan m2 chip is RISCV based, pretty cool
January 9, 2026 at 10:52 PM
damn TIL the titan m2 chip is RISCV based, pretty cool
I just had a conversation that ranged from RISCV debugging to Camus, self worth, actualization, Skinner boxes, and programming language theory, AMA
November 11, 2025 at 7:27 PM
I just had a conversation that ranged from RISCV debugging to Camus, self worth, actualization, Skinner boxes, and programming language theory, AMA
that said, a riscv mainboard wouldn't go amiss.......
February 26, 2025 at 11:35 AM
that said, a riscv mainboard wouldn't go amiss.......
is it stolen valor if I put a cool "riscv inside" sticker on my amd64 laptop
April 2, 2026 at 6:05 AM
is it stolen valor if I put a cool "riscv inside" sticker on my amd64 laptop
Learn RISC-V
A community-driven compilation of RISC-V resources and learning material.
github.com/riscv/learn
A community-driven compilation of RISC-V resources and learning material.
github.com/riscv/learn
January 14, 2025 at 12:48 AM
Learn RISC-V
A community-driven compilation of RISC-V resources and learning material.
github.com/riscv/learn
A community-driven compilation of RISC-V resources and learning material.
github.com/riscv/learn
Weekend project: I’ve been studying RISC-V by building an emulator. Here’s the result: a pure #Python #RISCV #emulator implementing RV32I + Zicsr. Passes the rv32ui & rv32mi tests from @riscv.org.web.brid.gy Runs Newlib programs, #MicroPython, #CircuitPython, #FreeRTOS.
github.com/ccattuto/ris...
github.com/ccattuto/ris...
GitHub - ccattuto/riscv-python: RISC-V Emulator in pure Python (RV32I, machine mode, Newlib support, memory-mapped IO)
RISC-V Emulator in pure Python (RV32I, machine mode, Newlib support, memory-mapped IO) - ccattuto/riscv-python
github.com
May 25, 2025 at 9:30 AM
Weekend project: I’ve been studying RISC-V by building an emulator. Here’s the result: a pure #Python #RISCV #emulator implementing RV32I + Zicsr. Passes the rv32ui & rv32mi tests from @riscv.org.web.brid.gy Runs Newlib programs, #MicroPython, #CircuitPython, #FreeRTOS.
github.com/ccattuto/ris...
github.com/ccattuto/ris...
riscv is already the most iso-brained instruction set of all time
August 24, 2026 at 6:26 AM
riscv is already the most iso-brained instruction set of all time
RISC-V Mainboard for Framework Laptop 13 Available from $199 www.omgubuntu.co.uk/2024/11/risc... #riscv #opensource
November 20, 2024 at 4:42 PM
RISC-V Mainboard for Framework Laptop 13 Available from $199 www.omgubuntu.co.uk/2024/11/risc... #riscv #opensource
Avrupa'daki riscv birleşik projesinin ctosu bir Türk. Riscv ABD tekelini kırmak için güzel bir proje
January 8, 2025 at 2:56 PM
Avrupa'daki riscv birleşik projesinin ctosu bir Türk. Riscv ABD tekelini kırmak için güzel bir proje
So today I’ve added a wooden shelf and wheels to my RiscV core; It’s a lot more practical now!
April 2, 2023 at 6:43 PM
So today I’ve added a wooden shelf and wheels to my RiscV core; It’s a lot more practical now!
Embedded-Swift-only RISC-V OS kernel 🤯
GitHub - MauriceElliott/MAGIos: A RISCV 64-bit operating system kernel written in Swift, inspired by the aesthetics and themes of Neon Genesis Evangelion.
A RISCV 64-bit operating system kernel written in Swift, inspired by the aesthetics and themes of Neon Genesis Evangelion. - MauriceElliott/MAGIos
github.com
September 23, 2025 at 3:46 PM
Embedded-Swift-only RISC-V OS kernel 🤯
RISC-V CEO Calista Redmond resigns after 5+ years of progress
riscv.org/riscv-news/2...
#RISCV #HPC #AI
riscv.org/riscv-news/2...
#RISCV #HPC #AI
RISC-V CEO Calista Redmond resigns after 5+ years of progress – RISC-V International
riscv.org
December 13, 2024 at 5:17 PM
RISC-V CEO Calista Redmond resigns after 5+ years of progress
riscv.org/riscv-news/2...
#RISCV #HPC #AI
riscv.org/riscv-news/2...
#RISCV #HPC #AI
Yeah, interrupts not being consistent between vendors is a huge heartbreak for riscv
December 27, 2024 at 8:38 PM
Yeah, interrupts not being consistent between vendors is a huge heartbreak for riscv
Doom läuft auf allem, auch in PDF – warum nicht auch Linux? Das dachte sich ein Tüftler und startet ein Minimalsystem im PDF-RISCV-Emulator. #Linux
Linux läuft im PDF
Doom läuft auf allem, auch in PDF – warum nicht auch Linux? Das dachte sich ein Tüftler und startet ein Minimalsystem im PDF-RISCV-Emulator.
www.heise.de
February 6, 2025 at 10:01 AM
Doom läuft auf allem, auch in PDF – warum nicht auch Linux? Das dachte sich ein Tüftler und startet ein Minimalsystem im PDF-RISCV-Emulator. #Linux
So now that video here is a thing, it should be easier to show what the breadboard RiscV looked like in full glory
September 15, 2024 at 7:22 AM
So now that video here is a thing, it should be easier to show what the breadboard RiscV looked like in full glory
RISCVという車のライセンスプレートを見かけた
April 6, 2024 at 7:51 PM
RISCVという車のライセンスプレートを見かけた
nintendo will be the first riscv console
December 13, 2023 at 8:11 AM
nintendo will be the first riscv console
I'm happy to release the next installment of 🏝️ Isle #FPGA computer with a #RISCV CPU design from @brunolevy01.bsky.social.
This chapter demonstrates how to interface a CPU with your own hardware and how to write bare-metal RISC-V assembly code for it.
projectf.io/isle/riscv-c...
This chapter demonstrates how to interface a CPU with your own hardware and how to write bare-metal RISC-V assembly code for it.
projectf.io/isle/riscv-c...
January 22, 2026 at 9:56 AM
I'm happy to release the next installment of 🏝️ Isle #FPGA computer with a #RISCV CPU design from @brunolevy01.bsky.social.
This chapter demonstrates how to interface a CPU with your own hardware and how to write bare-metal RISC-V assembly code for it.
projectf.io/isle/riscv-c...
This chapter demonstrates how to interface a CPU with your own hardware and how to write bare-metal RISC-V assembly code for it.
projectf.io/isle/riscv-c...